Planar Stacked Semiconductor Chips Reducing Package Size and Voids
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in efficiently integrating multiple high-capacity semiconductor chips in a limited space, leading to size constraints and potential reliability issues due to void formation and delamination.
Innovation Solution
A semiconductor package design featuring a substrate with two semiconductor chips stacked in a planar manner, using insulation adhesive and bonding wires that pass through the adhesive to electrically couple the chips, and an encapsulation member to protect the chips, which reduces the package size and prevents void formation by using a PWBL film and vent holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of stationary object
If multiple semiconductor chips are mounted on a small-sized substrate, then the package size is reduced, but void formation and delamination occur due to insufficient space between chips
Solution Approach 1:
The patent transitions from a conventional lateral arrangement of chips to a vertical stacking configuration. Multiple semiconductor chips are arranged in layers along the vertical dimension, allowing dense integration while maintaining adequate horizontal spacing between chips. This dimensional change enables reduced package footprint without compromising reliability through proper spacing for adhesive application and void prevention.
Solution Approach 2:
The patent implements a nested structure where semiconductor chips are stacked vertically one above another, with each chip nested in relation to the substrate and other chips. The insulation adhesive nests between the chips and substrate, creating a compact hierarchical arrangement that maximizes space utilization while maintaining structural integrity and preventing delamination through proper adhesive distribution.
2Volume of stationary object
If bonding wires are arranged densely to connect multiple chips, then the package size is reduced, but manufacturing precision and reliability deteriorate due to wire interference and difficulty in formation
Solution Approach 1:
The patent resolves wire interference issues by utilizing the vertical dimension for wire routing. Bonding wires connect chips across vertical layers, allowing connections without lateral interference between wires. This three-dimensional wire arrangement enables dense chip packaging while maintaining adequate wire spacing and formation precision, as wires can be routed through different vertical levels rather than competing for the same lateral space.
3Reliability
If additional space is provided between chips for adhesive application, then void formation is prevented, but the package size increases
Solution Approach 1:
The patent moves the spacing requirement from the lateral dimension to the vertical dimension. By stacking chips vertically, the horizontal footprint is minimized while maintaining adequate vertical spacing between chips for proper adhesive application. This allows the adhesive to be applied effectively in the vertical gaps between stacked chips, preventing void formation without increasing the overall package footprint.
Solution Approach 2:
The patent employs thin film insulation adhesive to bond chips in the vertical stacking configuration. The thin film nature of the adhesive allows it to be applied in the limited vertical gaps between chips while maintaining effective bonding and preventing void formation. This thin film approach enables reliable adhesive application in the constrained vertical space without requiring excessive chip separation.
Data Source
AI summary
A semiconductor package may be provided. A semiconductor package may include a substrate. The semiconductor package may include a first semiconductor chip and a second semiconductor chip which are disposed adjacent to each other over a first surface of the substrate. The semiconductor package may include first bonding wires which electrically couple the first semiconductor chip and the substrate. The semiconductor package may include an insulation adhesive which is interposed between the second semiconductor chip and the substrate. The first bonding wires may be disposed to pass through the insulation adhesive and electrically couple the first semiconductor chip and the substrate.