Display Planarization Protrusions for Metal Residue Reduction
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Solution Overview
Problem
Electronic device displays face challenges in preventing moisture intrusion and ensuring reliable fabrication processes, particularly in forming structures like vias and trenches, which can lead to complexity and reliability issues.
Innovation Solution
The use of patterned organic planarization layers with protrusions and reduced via depths, along with metal and dielectric bumps, helps in forming reliable contacts and preventing shorts between metal lines by ensuring effective removal of planarization layer material and reducing the risk of moisture intrusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If vias are reduced in depth by forming metal bumps and dielectric bumps, then metal can effectively extend down the sidewalls to form contacts, but the process complexity increases
Solution Approach 1:
Metal bumps and dielectric bumps are formed in advance before via etching to pre-establish the contact structure and reduce via depth, enabling metal to effectively extend down sidewalls and form reliable contacts without requiring deeper via etching processes
2Object-affected harmful factors
If planarization layer material is removed to form trenches, then moisture intrusion is prevented, but steps are formed that can cause metal residue and shorts
Solution Approach 1:
Trenches are divided into multiple trench segments with non-trenched areas between them, allowing metal lines to pass through without crossing planarization layer steps, thereby eliminating metal residue accumulation points and preventing shorts while maintaining moisture barrier functionality
Solution Approach 2:
The planarization layer is selectively removed only in specific trench regions while leaving non-trenched areas intact, creating localized moisture protection zones without forming problematic steps that would cause metal residue and shorts
3Reliability
If protrusions are added to planarization layer steps to eliminate metal residue, then shorts between lines are prevented, but the process complexity increases
Solution Approach 1:
Instead of modifying step geometry with protrusions, the planarization layer is segmented into trenched and non-trenched areas, eliminating the need for protrusions and their associated process complexity while achieving the same short prevention goal
Data Source
AI summary
Thin-film transistor circuitry for a display may include conductive layers such as transparent conductive layers and metal layers and may include dielectric layers. The dielectric layers may include buffer layers, interlayer dielectric, gate insulator, and organic planarization layers. The organic planarization layers may be patterned photolithographically to form vias, trenches, and other structures. Trenches may be formed by removing the planarization layer in a strip. When planarization material is removed for forming a trench or other structure, a step is formed in the planarization material. Metal lines such as data lines and other signal lines may cross steps in the planarization material. To prevent shorts between lines, a step may have protrusions that help eliminate metal etch residue. Vias may be reduced in depth by forming metal bumps and dielectric bumps under the vias and by forming other via structures.