Planarized Gate Structure for Memory Integration
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Solution Overview
Problem
Integrating split-gate memory cells with other field-effect devices on the same substrate is challenging due to different fabrication parameters required for each type, affecting cost, performance, and manufacturability.
Innovation Solution
A semiconductor device is formed with a gate structure that includes a charge trapping dielectric between the substrate and a first poly layer, a sidewall dielectric on the poly layer, and a second poly layer with a vertical portion in contact with the sidewall dielectric and a top portion that is substantially flat, facilitating efficient integration of memory cells with non-memory transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If split-gate memory cells are integrated with non-memory field-effect devices on the same substrate, then device functionality and performance are improved, but fabrication complexity increases due to different fabrication parameters required for each device type
Solution Approach 1:
The substrate is divided into a memory cell region and a non-memory device region, with each region having its own optimized gate structure and fabrication parameters. Memory cells use a first gate structure with specific dimensions and materials, while non-memory devices use a second gate structure with different dimensions and materials, allowing independent optimization of each device type without compromising the other.
Solution Approach 2:
Different gate structures are provided in different regions of the substrate according to local requirements. The memory cell region receives a gate structure optimized for memory operation characteristics, while the non-memory device region receives a gate structure optimized for logic or other functions. This localized optimization enables each device type to achieve its best performance while coexisting on the same substrate.
2Ease of manufacture
If different gate structures are provided in different regions, then integration of memory and non-memory devices is facilitated, but process complexity increases
Solution Approach 1:
A gate dielectric layer is formed across the entire substrate before region-specific gate structures are created. This preliminary formation of the gate dielectric layer provides a common foundation for both memory and non-memory devices, reducing process complexity by establishing shared infrastructure before diverging into region-specific fabrication steps.
Solution Approach 2:
The gate dielectric layer serves as an intermediary structure that is common to both memory cell regions and non-memory device regions. This intermediate layer enables different gate structures to be formed on the same substrate while maintaining electrical isolation and providing a uniform interface for subsequent processing steps, thereby simplifying the overall integration process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient integration of memory cells and non-memory devices on the same substrate, improving cost, performance, and manufacturability by optimizing the fabrication process and device structure.
Implementation Method 1
A non-volatile memory cell stores data, for example, by storing electrical charge in an electrically isolated floating gate or in a charge-trapping layer underlying a control gate of a field-effect transistor (FET)
Implementation Method 2
A non-volatile memory cell is programmed using, for example, hot carrier injection to place charge into a storage layer. High drain and gate voltages are used to facilitate the programming process, and the memory cell conducts relatively high current during programming
Implementation Method 3
Since acceleration of the carriers takes place in the channel region mostly under the select gate, the relatively low voltage on the select gate results in more efficient carrier acceleration in the horizontal direction compared to a conventional Flash memory cell
Data Source
AI summary
Semiconductor devices and methods of producing the devices are disclosed. The devices are formed by forming a gate structure on a substrate. The gate structure includes a charge trapping dielectric formed between the substrate and a first poly layer. A top dielectric is formed over the poly layer and a sidewall dielectric is formed on a side of the poly layer. A second poly layer is formed over the gate structure such that a portion of the second poly layer includes a vertical portion that is in contact with the sidewall dielectric and a top portion that is in contact with the top dielectric. The top portion of the second poly layer can then be removed through, for instance, planarization.