Planarized Wiring Layer for Substrate Bonding Integrity
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Solution Overview
Problem
Current methods for bonding substrate surfaces in semiconductor fabrication, such as Silicon-on-Sapphire (SOS) technology, face challenges in achieving improved bonding integrity and extending the capabilities of bonded substrate manufacturing.
Innovation Solution
A method involving planarization of the wiring layer on a device substrate, followed by removably bonding a temporary handle wafer and then bonding the substrate's opposite surface to a final handle substrate, enhances bonding integrity by using a temporary handle substrate for mechanical support during the bonding process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thin layer of silicon is deposited onto a bulk sapphire wafer at high temperature, then Silicon-on-Sapphire substrate can be formed, but bonding integrity and manufacturing capabilities are limited
Solution Approach 1:
The substrate structure is segmented into multiple layers: a final handle substrate, a device substrate with device structures, and an interconnect structure with planarized wiring layers. This segmentation allows each layer to be optimized independently and bonded together with improved integrity while enabling complex manufacturing capabilities.
Solution Approach 2:
The planarized wiring layer acts as an intermediary bonding interface between the device substrate and the final handle substrate. By planarizing the wiring layer, a flat bonding surface is created that improves bonding integrity while the multi-layer structure provides enhanced manufacturing versatility.
2Reliability
If conventional substrate bonding methods are used, then manufacturing process is simple, but bonding integrity is insufficient
Solution Approach 1:
The wiring layer is planarized before the final bonding step. This preliminary action creates a flat bonding surface that significantly improves bonding integrity. The temporary handle wafer is also used in advance to support the structure during processing.
Solution Approach 2:
The planarized wiring layer serves as an intermediary bonding interface that improves contact between substrates. The temporary handle wafer acts as another intermediary that provides mechanical support during the bonding process and can be removed afterward.
3Reliability
If device structures and interconnect structures are formed on substrate, then functional circuits are created, but surface non-planarity reduces bonding quality
Solution Approach 1:
The wiring layer is planarized using chemical mechanical polishing (CMP) or etch-back processes before bonding. This preliminary planarization removes surface non-planarity caused by device structures and interconnect features, creating a flat bonding surface that improves bonding quality.
Solution Approach 2:
The surface topology is changed from non-planar to planar through the planarization process. This parameter change in surface flatness directly improves bonding quality while preserving the underlying device structures and interconnect features.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the bonding integrity of substrates, allowing for the creation of high-performance radio-frequency integrated circuits with enhanced mechanical and electrical properties.
Implementation Method 1
In response to planarizing the wiring layer, a temporary handle wafer is removably bonded to the wiring layer
Implementation Method 2
In response to removably bonding the temporary handle wafer to the wiring layer, the second surface of the device substrate is bonded to a final handle substrate
Data Source
AI summary
Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.