Plasma Trim Control for Core Critical Dimension Uniformity
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in controlling core critical dimension uniformity across and between wafers due to variations in plasma etching results, leading to device failure and performance issues.
Innovation Solution
A method is introduced to control core critical dimension by determining specific plasma trim process parameters based on target trim amounts and profiles, using data correlations to achieve uniformity across and between wafers, involving a base trim process and a wafer-specific flash trim process in multiple plasma processing stations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If plasma etching process is used to remove material from semiconductor wafer, then material removal efficiency is improved, but critical dimension uniformity deteriorates due to plasma etching variations
Solution Approach 1:
The patent segments the critical dimension control process into multiple independent stages: initial photolithography patterning, followed by separate trim processes (first trim, second trim, and flash trim) that can be individually optimized and controlled. This segmentation allows each stage to contribute to the final critical dimension without compounding variations from a single aggressive etching step.
Solution Approach 2:
The patent employs parameter changes by adjusting plasma process conditions (power, pressure, gas flow rates, temperature) across different trim stages to achieve varying levels of material removal. Each trim process uses specific parameter settings tailored to its function, enabling precise control over critical dimension while maintaining manufacturing efficiency.
2Productivity
If aggressive plasma etching is used to increase material removal rate, then productivity is improved, but critical dimension control precision deteriorates
Solution Approach 1:
The patent applies preliminary action by performing initial patterning and first trim processes that prepare the structure for subsequent more precise trim operations. These preliminary steps remove the bulk of material needed to be removed, setting up the structure for finer adjustments in later stages without requiring the final trim processes to work as aggressively.
Solution Approach 2:
The patent uses periodic action through multiple discrete trim processes (first trim, second trim, flash trim) separated by intermediate steps. Each trim process operates periodically rather than as a single continuous aggressive etching step, allowing for intermediate measurements and adjustments that maintain precision while achieving overall high material removal.
3Manufacturing precision
If multiple trim processes are implemented to improve critical dimension uniformity, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The patent applies universality by using the same basic plasma etching equipment and process platform for all trim operations (first trim, second trim, and flash trim). This multi-functional approach allows a single type of equipment to perform multiple trim functions with different parameter settings, reducing the need for additional specialized equipment while maintaining precision.
Solution Approach 2:
The patent implements feedback through critical dimension measurements taken at various stages (after photolithography, after first trim, after second trim) that inform subsequent process adjustments. This feedback loop allows each subsequent trim process to be optimized based on actual measurements from previous steps, improving uniformity while systematically managing process complexity through data-driven control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces and eliminates critical dimension non-uniformity and imbalance, ensuring consistent core feature dimensions across and between wafers, thereby enhancing device reliability and performance.
Implementation Method 1
Plasma etching processes are often used in the manufacture of semiconductor devices. In the plasma etching process, a semiconductor wafer that includes semiconductor devices under manufacture is exposed to a plasma that interacts with at least one material on the semiconductor wafer so as to remove the at least one material.
Implementation Method 2
a bias voltage can be applied to the semiconductor wafer to enable anisotropic etching of features on the semiconductor wafer by attracting charged constituents of the plasma toward the semiconductor wafer in a more perpendicular direction
Data Source
AI summary
A pattern of core material is formed on a wafer to include core features that have a critical dimension. A trim amount indicates an average amount of thickness to be removed from vertically oriented surfaces of the core features. A trim profile indicates how much variation in removal of thickness from vertically oriented surfaces of the core features is to be applied as a function of radial location on the wafer. A first set of data correlates the trim amount to one or more plasma trim process parameters. A second set of data correlates the trim profile to one or more plasma trim process parameters. Based on the trim amount, trim profile, and first and second sets of data, a set of plasma trim process parameters to achieve the trim amount and trim profile on the wafer is determined and a corresponding plasma trim process is performed on the wafer.