Platable Dielectric Circuit Structure for Sub-40 Micrometer Line Widths

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional circuit fabrication techniques are limited by the uniformity of electroplating and photolithography processes, making it difficult to achieve line widths smaller than 40 micrometers, resulting in poor product yield and high costs.

Innovation Solution

A circuit structure with a conductive via and trench pattern on a platable dielectric layer, using laser-processable materials to form a conductive pattern without photolithography, allowing for line widths smaller than 40 micrometers by controlling the trench pattern width.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional electroplating and photolithography processes are used, then the manufacturing process is simple and well-established, but the line width cannot be smaller than 40 micrometers and manufacturing precision deteriorates

Engineering Contradiction:
Improveline widthVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent changes the fundamental parameters of the manufacturing process by replacing photolithography with laser processing and conventional electroplating with chemical plating. This parameter change enables line widths smaller than 40 micrometers to be achieved, directly resolving the contradiction between manufacturing precision and device complexity.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent substitutes the photolithography process (optical/mechanical system) with a laser-based process. The laser process allows for more precise control of line width and pattern formation, enabling sub-40 micrometer features while maintaining process feasibility through automated laser scanning and processing.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Area of moving object

If line width is decreased to increase layout density, then layout density is improved, but manufacturing precision and product yield deteriorate due to process limitations

Engineering Contradiction:
Improvelayout densityVSAvoidline width uniformity
Core Design Contradiction:
Area of moving objectVSManufacturing precision

Solution Approach 1:

By changing from electroplating to chemical plating, the patent achieves more uniform metal layer deposition at smaller line widths. The chemical plating process provides better control over thickness and uniformity, enabling high layout density with maintained manufacturing precision and improved product yield.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves process yield and reduces costs by enabling the formation of conductive patterns with line widths less than 40 micrometers, eliminating the need for photolithography and enhancing layout density on circuit boards.

Implementation Method 1

a material of the platable dielectric layer includes a chemical platable material

Methodology Applied
Scientific EffectChemical plating: Chemical Beam Epitaxy

Implementation Method 2

a material of the platable dielectric layer comprises a laser-processable material

Methodology Applied
Scientific EffectLaser ablation: Laser Ablation

Data Source

PatentUS8288662B2Circuit structure
Publication Date: 2012.10.16 UNIMICRON TECH CORP
  • US8288662B2 patent drawing
  • US8288662B2 patent drawing

AI summary

A circuit structure including a circuit board, an insulating layer, a conductive via, a platable dielectric layer and a conductive pattern is provided. The insulating layer is disposed on the circuit board and covers a circuit layer of the circuit board. The conductive via passes through the insulating layer and connects the circuit layer and protrudes from a surface of the insulating layer. The platable dielectric layer having a trench pattern is disposed on the surface of the insulating layer wherein the portion of the conductive via protruding from the surface is located in the trench pattern. The material of the platable dielectric layer includes a chemical platable material. The conductive pattern is in the trench pattern and connects the conductive via wherein an interface exists between the conductive pattern and the conductive via and protrudes from the surface of the insulating layer.