Programmable Logic Device Distributed Memory Architecture
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Solution Overview
Problem
Conventional programmable logic devices face limitations due to insufficient embedded volatile memory, leading to routing congestion and inflexibility in memory allocation, with the distributed memory approach often resulting in unused resources and an undesirable reliance on external bitstream programming.
Innovation Solution
A programmable logic device architecture that incorporates non-volatile memory for storing configuration data, allowing for flexible distribution of random access memory functionality across logic blocks, decoupling memory from logic to optimize resource allocation and reduce routing congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If embedded blocks of volatile memory are used, then temporary storage during operation is provided, but routing congestion occurs and memory capacity is insufficient
Solution Approach 1:
The patent divides memory functionality into two types: embedded volatile memory blocks for temporary storage and distributed memory within logic blocks for application-specific storage. This segmentation allows memory to be distributed throughout the device rather than concentrated in large blocks, reducing routing congestion while providing sufficient total capacity.
Solution Approach 2:
The patent transitions from a centralized memory architecture (large embedded blocks) to a distributed memory architecture (memory cells within each logic block). This dimensional change from集中式 to distributed architecture eliminates routing congestion by placing memory resources at the location where they are needed, eliminating long interconnect paths.
2Quantity of substance
If distributed memory approach is used, then memory capacity is increased, but unused circuitry and resources result
Solution Approach 1:
The patent implements dynamic memory allocation where the amount and distribution of memory resources can be configured based on specific application requirements. During device programming, memory cells are allocated only where needed, allowing the system to adapt to different applications and eliminate unused resources through configurable memory distribution.
3Adaptability or versatility
If conventional distributed memory is used, then memory flexibility is improved, but programming complexity increases due to external bitstream requirements
Solution Approach 1:
The patent implements self-service programming where configuration data is automatically loaded from non-volatile memory cells during device initialization, eliminating the need for external bitstream programming. The device configures itself by reading configuration data from its internal non-volatile memory, simplifying the programming process while maintaining flexible memory allocation.
4Adaptability or versatility
If homogeneous logic blocks with distributed memory are used, then routing flexibility is improved, but resource efficiency decreases
Solution Approach 1:
The patent implements heterogeneous logic blocks with varying memory capacities rather than homogeneous blocks. Each logic block can be configured with the specific amount of memory needed for its function, allowing optimal resource utilization. This local differentiation ensures that routing flexibility is maintained while eliminating the resource waste associated with uniform block designs.
Data Source
AI summary
Systems and methods are disclosed herein in accordance with one or more embodiments of the present invention to provide programmable logic devices with non-volatile memory and a variable amount of distributed memory (e.g., in a cost-effective manner). For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of input/output blocks providing an input/output interface for the programmable logic device and a first and second plurality of logic blocks providing programmable logic functions, with only the second plurality of logic blocks further adapted to provide random access memory functions. A routing structure programmably interconnects the input/output blocks and the first and second plurality of logic blocks. Configuration memory cells store configuration data to configure the input/output blocks, the first and second plurality of logic blocks, and the routing structure, with at least one block of non-volatile memory to store configuration data that can be transferred to the configuration memory cells.