PLD Structure Using Third Dimensional Memory for Reprogrammability
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Solution Overview
Problem
Conventional Programmable Logic Devices (PLDs) using fuse blowing and anti-fuse technologies are non-reprogrammable, result in high dead-on-arrival rates, and cannot be integrated into standard CMOS designs, limiting their flexibility and application.
Innovation Solution
A Programmable Logic Device structure utilizing a non-volatile third-dimensional memory array with two-terminal memory elements and mixed valence conductive oxides, allowing for dynamic reprogramming and integration with standard CMOS processes by controlling input selection with non-volatile registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If fuse blowing technology is used for input selection, then connections can be established between inputs and logic gates, but the device becomes non-reprogrammable and requires high voltage circuitry
Solution Approach 1:
The patent replaces static fuse-based connections with dynamic, reconfigurable connections using non-volatile memory elements that can be programmed and reprogrammed. The memory elements allow the connection topology to change over time, enabling the device to be reconfigured for different logic functions after initial programming.
Solution Approach 2:
The patent changes the electrical parameters of the connection medium by using non-volatile memory elements with switchable resistance states. These memory elements can transition between high-resistance (open) and low-resistance (closed) states, providing a reconfigurable connection mechanism that eliminates the need for destructive fuse blowing while maintaining connection integrity.
2Ease of manufacture
If anti-fuse technology is used for input selection, then connections can be established between inputs and logic gates, but the device becomes non-reprogrammable and cannot be tested before final programming
Solution Approach 1:
The patent enables preliminary testing and configuration by allowing the non-volatile memory elements to be programmed and tested before final device deployment. The reprogrammable nature of the memory elements permits multiple programming attempts and functional verification, eliminating the risk of permanent defects that plague anti-fuse technology.
Solution Approach 2:
The non-volatile memory elements inherently provide their own non-volatile storage capability, eliminating the need for separate volatile memory and associated refresh circuitry. This self-contained approach reduces overall device complexity and improves reliability by removing components that could fail.
3Ease of operation
If conventional PLD structures are used, then logic functions can be implemented, but high voltage charge pumps are required increasing device complexity
Solution Approach 1:
The patent extracts and removes the high voltage charge pump circuitry from the PLD structure by using non-volatile memory elements that can be programmed with standard CMOS-compatible voltages. This extraction eliminates the complex high voltage generation circuitry while preserving the essential programming functionality through the memory elements' inherent non-volatile storage capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reprogrammability, reduces circuitry costs, improves reliability, and allows PLDs to be used across a wider range of applications by eliminating the need for high voltage charge pumps and enabling dynamic routing function changes.
Implementation Method 1
The memory element includes an electrolytic tunnel barrier and a mixed valence conductive oxide. The voltage drop across the electrolytic tunnel barrier causes an electrical field within the mixed valence conductive oxide that is strong enough to move oxygen ions
Implementation Method 2
The memory element includes an electrolytic tunnel barrier and a mixed valence conductive oxide. Oxygen depletion causes the mixed valence conductive oxide to change its valence, which causes a change in conductivity
Implementation Method 3
The voltage drop across the electrolytic tunnel barrier causes an electrical field within the mixed valence conductive oxide that is strong enough to move oxygen ions out of the mixed valence conductive oxides and into the electrolytic tunnel barrier
Data Source
AI summary
A Programmable Logic Device (PLD) structure using third dimensional memory is disclosed. The PLD structure includes a switch configured to couple a polarity of a signal (e.g., an input signal applied to an input) to a routing line and a non-volatile register configured to control the switch. The non-volatile register may include a non-volatile memory element, such as a third dimension memory element. The non-volatile memory element may be a two-terminal memory element that retains stored data in the absence of power and stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage across the two terminals. Logic and other active circuitry can be positioned in a substrate and the non-volatile memory element can be positioned on top of the substrate.