Plesiochronous Receiver Pin Synchronous Testing Mode
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Solution Overview
Problem
Integrated circuits configured for plesiochronous communications face challenges in manufacturing tests due to the inability of automated test equipment to align test stimuli with the embedded clock signal, leading to misalignment issues and the need for expensive dedicated test pins, which limits testing capabilities.
Innovation Solution
The method involves using the same plesiochronous interconnects for both normal data reception and test stimulus data transmission by switching to a synchronous mode during testing, allowing test stimulus data to be conveyed synchronously over separate or dual single-ended channels, eliminating the need for dedicated test pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dedicated test pins are added for synchronous testing, then testing capability is improved, but device complexity and cost increase
Solution Approach 1:
The plesiochronous receiver pin is designed to perform dual functions: normal plesiochronous data reception during operational mode and synchronous test stimulus reception during testing mode. The receiver circuitry includes mode selection logic that routes incoming signals appropriately based on the operational state, eliminating the need for separate dedicated test pins while maintaining both testing capability and normal functionality
Solution Approach 2:
The receiver pin dynamically switches between plesiochronous reception mode and synchronous test mode based on operational requirements. The system includes mode control circuitry that can reconfigure the receiver's clocking and data sampling mechanisms to accommodate either embedded clock recovery for normal operation or reference clock synchronization for testing, allowing the same hardware to adapt to different operational modes
2Adaptability or versatility
If dedicated test pins are added for synchronous testing, then testing capability is improved, but pin count increases
Solution Approach 1:
The receiver pin serves multiple purposes by functioning as both a plesiochronous data input pin during normal operation and a synchronous test stimulus input pin during testing. This multi-functionality is achieved through mode-selectable receiver circuitry that can operate with either embedded clock recovery or reference clock synchronization, thereby eliminating the need for additional dedicated test pins and reducing the overall pin count requirement
3Speed
If plesiochronous reception is used, then data transfer speed is improved, but ease of operation deteriorates due to testing constraints
Solution Approach 1:
The receiver implements dynamic operational modes that allow switching between plesiochronous reception with embedded clock recovery for high-speed normal operation and synchronous reception with reference clock for simplified testing. The mode selection is controlled by internal logic that determines the appropriate reception mode based on the operational state, enabling the system to maintain high data transfer speeds during normal use while facilitating ease of operation during testing phases
4Speed
If plesiochronous reception is used, then data transfer speed is improved, but testing capability deteriorates
Solution Approach 1:
The receiver is designed with dynamic reconfigurability to switch between plesiochronous mode with embedded clock recovery for high-speed normal operation and synchronous mode with reference clock for comprehensive testing capability. The mode control mechanism enables the same hardware to adapt to different operational requirements, maintaining high data transfer speeds during normal use while providing full testing capability when needed
Solution Approach 2:
The receiver pin and associated circuitry are designed to perform multiple functions: plesiochronous data reception during normal operation and synchronous test stimulus reception during testing. This universality is achieved through mode-selectable circuitry that can operate with either embedded or reference clocks, thereby eliminating the trade-off between speed and testing capability
Data Source
AI summary
A method and apparatus for conveying test stimulus data from an ATE system to an integrated circuit (IC) via a plesiochronous interconnect. The IC includes a core logic unit and a first receiver coupled to the core logic unit by a first data path. The first receiver includes an input having an interconnect coupled thereto. In a normal mode of operation, the first receiver is configured to receive data transmitted plesiochronously over the interconnect and to convey the data, via the first data path, to the core logic unit. The integrated circuit also includes a second data path coupled between the core logic unit and the interconnect. In a test mode, the core logic unit is configured to receive test stimulus data conveyed synchronously over the second data path, wherein the test stimulus data is received by the IC from the ATE via the interconnect.