Array Substrate PLG Line Protection via Sealant Nesting
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Solution Overview
Problem
The existing Peripheral Layout Gate (PLG) lines in array substrates for TFT-LCD displays are prone to damage from external forces, scratches, or corrosion, leading to abnormal display due to disrupted signal transmission to the gate driving units.
Innovation Solution
The array substrate design includes signal connection lines with portions arranged in the peripheral region and sealant region, where the sealant covers the connection lines, and additional parallel connection lines for redundancy, using materials identical to the pixel electrode or conductive layers, and employing conductive metallic balls for secure connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the PLG line is arranged at the edge of the array substrate for signal transmission, then the gate driving unit can receive voltage and control signals, but the PLG line is easily damaged due to external force, scratch or corrosion
Solution Approach 1:
The PLG line is nested within the sealant structure, forming a protected pathway. The sealant acts as a protective enclosure that shields the PLG line from external environmental factors while maintaining electrical connectivity between driving units and gate electrodes
Solution Approach 2:
The sealant serves as an intermediary protective layer between the PLG line and the external environment. It mediates the conflict by providing mechanical protection and corrosion resistance while allowing the PLG line to fulfill its signal transmission function
2Ease of operation
If the PLG line is positioned at the peripheral region for connecting driving units, then signal transmission is enabled, but the line is vulnerable to damage and causes abnormal display
Solution Approach 1:
The PLG line is nested within the sealant structure, forming a protected pathway that maintains ease of signal transmission while shielding the line from damage that would cause abnormal display
3Ease of manufacture
If the array substrate area is made slightly greater than the color filter substrate for bonding space, then gate and source driving units can be bonded, but the additional peripheral region exposes connection lines to damage
Solution Approach 1:
The sealant performs multiple functions: it provides the bonding interface between substrates, creates a protective enclosure for the PLG line, and seals the liquid crystal display cavity. This multi-functionality allows the peripheral region to support bonding while protecting connection lines
Solution Approach 2:
The PLG line is nested within the sealant structure in the peripheral region, allowing the sealant to simultaneously provide bonding functionality and protective enclosure, thus resolving the conflict between manufacturing ease and protection from harmful factors
Data Source
AI summary
The present disclosure provides an array substrate, a display panel, manufacturing methods thereof and a display device. The array substrate includes a display region and a non-display region. The non-display region includes a sealant region arranged at a periphery of the display region and a peripheral region arranged at a periphery of the sealant region. The array substrate further includes a plurality of signal connection lines for connecting driving lines. The signal connection lines include a first connection line, a portion of which is arranged at the peripheral region and another portion of which is arranged at the sealant region.