PLL Calibration Using Descending Divider Codes to Avoid Overshoot
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Solution Overview
Problem
Phase-locked loops (PLLs) experience overshoot and glitch during calibration, which can induce computational errors or system failures, especially when transitioning between high and low frequency clock signals, and existing methods to mitigate these issues are inadequate.
Innovation Solution
A method that forces the control voltage of a voltage-controlled oscillator to a reference voltage, uses a calibration divider with multiple divisors to adjust the output clock signal frequency smoothly, and employs a frequency descending code to avoid overshoot, ensuring the PLL operates at a low frequency during calibration to prevent glitches and overshoot.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If frequency ascending code jumping is used during calibration, then calibration speed is improved, but overshoot occurs in the PLL output clock signal
Solution Approach 1:
The patent inverts the conventional calibration approach by using frequency descending code jumping instead of ascending. The calibration process starts from a high frequency calibration code and jumps down to lower frequency codes, which prevents overshoot in the PLL output clock signal while maintaining fast calibration speed through code jumping methodology.
Solution Approach 2:
The patent applies preliminary action by pre-selecting a high frequency calibration code as the starting point before beginning the calibration process. This preliminary setup ensures that subsequent code jumps will transition to lower frequencies, preventing overshoot conditions from occurring during calibration.
2Reliability
If frequency descending code is used during calibration, then overshoot is avoided, but calibration speed is reduced
Solution Approach 1:
The patent applies skipping by implementing code jumping methodology that allows the calibration process to rapidly transition between frequency codes. Instead of incrementing or decrementing by small steps, the calibration controller can jump directly to target calibration codes, significantly reducing calibration time while maintaining the frequency descending approach to avoid overshoot.
3Productivity
If calibration code jumps are made during calibration, then calibration efficiency is improved, but glitch occurs in the output clock signal
Solution Approach 1:
The patent inverts the calibration direction to frequency descending code jumping, which prevents glitch in the output clock signal during calibration code transitions. By transitioning from high to low frequency codes rather than low to high, the PLL output signal remains stable and free from glitch artifacts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces or eliminates glitches and overshoot during PLL calibration, providing a stable system clock that minimizes computational errors and ensures reliable operation by smoothly transitioning between divisors and maintaining a low frequency during calibration.
Implementation Method 1
a voltage controlled oscillator that generates an output clock signal in response to a control voltage
Implementation Method 2
a reference voltage regulator coupled to receive a reference voltage and to force the control voltage to the reference voltage upon receipt of a force signal
Data Source
AI summary
A method of calibrating a PLL that includes forcing a control voltage input to a voltage controlled oscillator to be a reference voltage and setting a calibration divider coupled to receive an output clock signal from the voltage controlled oscillator such that the calibration divider utilizes one of a plurality of divisors that results in the output clock signal having a high frequency can substantially avoid overshoot and glitch problems associated with conventional PLL calibrations.