PLL Resonant Circuit Calibration for Fast Radar Chirp Tuning
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Solution Overview
Problem
Conventional PLL circuits in radar systems require long calibration times, typically performed only at system startup, which is inefficient for real-time adjustments due to process, voltage, and temperature variations.
Innovation Solution
A tunable resonant circuit with a calibration circuit that selectively couples capacitances based on digital and analog control signals during dead times between chirp signals, allowing for fast and dynamic frequency tuning of the PLL circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional calibration techniques are used in PLL circuits, then frequency accuracy is improved, but calibration time increases significantly
Solution Approach 1:
The patent pre-charges the filter capacitor during the dead time interval between chirp signals using a dedicated charge pump circuit. This preliminary action ensures that when calibration is needed, the capacitor is already charged, eliminating the need for time-consuming charging operations during actual calibration steps.
Solution Approach 2:
The patent changes the operational state of the PLL by switching between different modes: during dead time, the system operates in a pre-charge mode where the capacitor is charged; during calibration, it switches to calibration mode where the pre-charged capacitor enables fast frequency adjustment. This parameter switching allows the system to achieve both speed and accuracy.
2Device complexity
If calibration is performed only at startup, then system complexity is reduced, but frequency stability deteriorates under PVT variations
Solution Approach 1:
The patent implements periodic calibration actions during dead time intervals between chirp signals. Instead of a single startup calibration, the system performs multiple quick calibration cycles at regular intervals, maintaining frequency stability under varying process, voltage, and temperature conditions without requiring a complex continuous calibration system.
Solution Approach 2:
The patent maintains continuous frequency stability through periodic calibration actions during operational dead times. The calibration function continues to be performed throughout system operation rather than being a one-time startup event, ensuring ongoing reliability while using simple circuitry.
3Productivity
If fast calibration is implemented during operation, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent makes the filter capacitor serve multiple functions: it acts as the filtering element during normal PLL operation and as a pre-charged energy source during calibration. This multi-functionality allows fast calibration without adding separate dedicated components, achieving high productivity while minimizing increased circuit complexity.
Solution Approach 2:
The charge pump circuit uses the existing filter capacitor to store charge that it then uses to quickly adjust the VCO frequency during calibration. The system essentially serves itself by using its own operational components for the calibration function, achieving fast calibration speed without proportionally increasing overall circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables rapid calibration of PLL circuits during operation, reducing calibration time and improving frequency stability in radar systems, particularly in automotive applications.
Implementation Method 1
A voltage-controlled oscillator (VCO) may be used in a FMCW radar detection system to generate variable frequency signals (e.g., to generate 'chirp' signals). The voltage-controlled oscillator may comprise a tunable LC resonant circuit.
Implementation Method 2
a phase-frequency detector circuit sensitive to an input reference signal and to the variable-frequency output signal and configured to generate a first digital control signal and a second digital control signal as a function of a timing offset of the variable-frequency output signal with respect to the input reference signal
Implementation Method 3
a charge pump circuit and a filter circuit configured to generate the control signal as a function of the first digital control signal and the second digital control signal
Implementation Method 4
a charge pump circuit and a filter circuit configured to generate the control signal as a function of the first digital control signal and the second digital control signal
Implementation Method 5
A tunable resonant circuit with a calibration circuit that selectively couples capacitances based on digital and analog control signals during dead times between chirp signals, allowing for fast and dynamic frequency tuning of the PLL circuit.
Data Source
AI summary
A circuit includes a phase-frequency-detector generating first and second digital control signals indicative of phase differences between an input reference-signal and an output-signal, a charge-pump generating a control-signal based upon the first and second digital control signals, and an oscillator-circuit. The oscillator-circuit includes an active core coupled between first and second nodes, with a tunable resonant circuit a set of capacitances selectively connected between the first and second nodes, wherein a tap between the first and second variable capacitances receives the control-signal for tuning the tunable resonant circuit. A timer-circuit generates a timing-signal based upon the input reference-signal and a reset-signal. A calibration-circuit controls which capacitances of the set of capacitances are connected between the first and second nodes, in response to the timing-signal and a comparison between a threshold and a voltage-signal that is based upon auxiliary pulsed currents generated based upon the first and second digital control signals.