PLL Clock Generation With Duty Cycle Adjustment for Fine Granularity
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Solution Overview
Problem
Integrated circuits face limitations in providing a wide range of clock frequencies due to the granularity of digital frequency synthesizer (DFS) circuits, which are costly and difficult to meet timing specifications, especially when requiring multiple clock frequencies for various subsystems with different operational needs.
Innovation Solution
The implementation of a phase-locked loop (PLL) with a voltage-controlled oscillator (VCO) and a duty cycle adjustment (DCA) circuit, along with an enable pattern generator, allows for the production of clock signals with adjustable frequencies and balanced or unbalanced duty cycles by selectively combining VCO phase outputs and adjusting the falling edge of the clock signal based on an enable signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If more phase outputs are provided from the VCO to improve granularity, then clock frequency resolution is improved, but circuit area and power consumption increase
Solution Approach 1:
The patent segments the frequency synthesis function into two stages: first, a clock divider circuit generates a first clock signal with lower resolution using fewer VCO phase outputs; second, a duty cycle adjustment circuit refines the frequency resolution by adjusting the duty cycle of the first clock signal to generate a second clock signal with higher resolution. This segmentation allows achieving fine granularity without proportionally increasing the number of VCO phase outputs, thereby reducing circuit area and power consumption.
2Measurement precision
If more phase outputs are provided from the VCO to improve granularity, then clock frequency resolution is improved, but power consumption increases
Solution Approach 1:
The patent segments the frequency synthesis function into two stages: first, a clock divider circuit generates a first clock signal with lower resolution using fewer VCO phase outputs; second, a duty cycle adjustment circuit refines the frequency resolution by adjusting the duty cycle of the first clock signal to generate a second clock signal with higher resolution. This segmentation allows achieving fine granularity without proportionally increasing the number of VCO phase outputs, thereby reducing circuit area and power consumption.
3Adaptability or versatility
If a clock divider circuit is used to produce selectable clock periods, then clock frequency adjustability is improved, but timing specifications become difficult to meet
Solution Approach 1:
The patent introduces a duty cycle adjustment circuit as an intermediary between the clock divider circuit and the final clock output. The clock divider circuit first generates a first clock signal with adjustable frequency but potentially non-compliant timing characteristics. The duty cycle adjustment circuit then refines this signal by adjusting the duty cycle to meet precise timing specifications, generating a second clock signal that satisfies both frequency adjustability and timing requirements.
4Adaptability or versatility
If oscillator circuits are designed to supply multiple different frequencies, then adaptability to different subsystem needs is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal oscillator circuit that can supply multiple different frequencies through a single integrated system. The clock divider circuit receives a selected subset of VCO phase outputs and generates a first clock signal at a frequency determined by the division ratio. The duty cycle adjustment circuit then refines this to produce a second clock signal with precise timing characteristics. This multi-functional design allows a single oscillator circuit to serve multiple subsystems with different frequency requirements, reducing overall system complexity compared to having separate oscillators for each frequency.
Data Source
AI summary
An oscillator circuit includes a phase-locked loop (PLL) with a plurality of voltage controlled oscillator (VCO), a clock divider circuit receiving the VCO phase outputs and outputting a first stage clock signal with an adjustable clock period related to the PLL period based on selecting a combination of two of the VCO phase outputs. The first stage clock signal has a balanced duty cycle at frequencies that are related to the PLL frequency by even fractional divisions of the VCO phase output period based on the quantity VCO phase outputs, and an unbalanced duty cycle at frequencies that are related by odd fractional divisions. A duty cycle adjustment (DCA) circuit receives the first stage clock signal selectively adjusts a falling edge of the first stage clock signal to provide an even duty cycle and feeds a resulting signal to the second stage clock signal output.