PLL Clock Gating for Near-Integer Spur Mitigation
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Solution Overview
Problem
Phase-locked loops, particularly All-Digital PLLs, experience performance degradation due to near-integer channel spurs, which cause spur frequency components to be coupled with the reference clock frequency, leading to unfiltered low-frequency spurs that degrade phase noise and Error Vector Magnitude (EVM) in communication systems.
Innovation Solution
The implementation of a clock gating circuit in the phase-locked loop that relocates spur frequency components outside the loop's cut-off frequency by speeding up phase variations at zero-crossings, allowing for effective filtering of these spurs through the loop filter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the phase-locked loop operates in near-integer channel conditions, then the loop can maintain frequency locking, but spur frequency components are coupled to the reference clock input causing phase noise and EVM degradation
Solution Approach 1:
The patent extracts and removes the harmful spur frequency components from the reference clock input by detecting their presence in near-integer channel conditions and actively canceling or filtering them out, preventing their coupling into the PLL system while maintaining normal frequency locking operation
Solution Approach 2:
The patent applies preliminary anti-action by preemptively identifying near-integer channel conditions and implementing countermeasures against spur generation before the spurs can couple into the system and degrade performance, thereby preventing the harmful effect rather than correcting it after occurrence
2Object-affected harmful factors
If the cut-off frequency of the loop filter is reduced to filter spurs, then phase noise is improved, but the loop response time increases and tracking performance degrades
Solution Approach 1:
The patent segments the frequency filtering function into two parts: the loop filter handles low-frequency phase noise filtering, while a separate spur filtering mechanism specifically targets and removes high-frequency spur components, allowing each filter to be optimized for its specific frequency range without compromising overall performance
Solution Approach 2:
The patent introduces an intermediary spur detection and cancellation mechanism that acts between the reference clock input and the loop filter, selectively removing spur frequency components before they enter the main PLL loop, thereby enabling aggressive low-pass filtering without sacrificing response time
Data Source
AI summary
A method includes relocating, to a frequency outside a cut-off frequency of a phase-locked loop, a spur frequency component at an input of the phase-locked loop coupled thereto due to an interference of a divided frequency component of an output frequency of the phase-locked loop with a reference clock frequency input thereto through a feedback path thereof when there is a near-integer relationship between the reference clock frequency input and the output frequency. The method also includes filtering the spur frequency component through the phase-locked loop.