PLL Clock Alignment Circuit for Parallel Data Reclocking
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Solution Overview
Problem
Existing systems face challenges in processing data signals when the rising edges of clock and data signals are coincident, and delay locked loops may not be available or introduce jitter, especially with high power consumption and restrictive operating parameters.
Innovation Solution
A system comprising a clock shifting circuit with a phase locked loop (PLL) and D flip flops, along with a data clocking circuit, is used to align clock and data signals by generating shifted clock signals that are phase-shifted relative to the incoming clock, allowing for reclocking of data bits without coincident rising edges, utilizing a PLL with feedback and combinatorial logic to manage signal alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a delay locked loop is used to retime clock signals, then the clock phase can be adjusted, but the system introduces jitter into the clock signal and consumes high power
Solution Approach 1:
The circuit segments the clock signal adjustment into discrete steps using individual delay elements (inverters) that can be selectively enabled or disabled. Instead of using a continuous delay locked loop, the patent divides the delay adjustment into manageable segments controlled by separate control signals, allowing precise phase alignment without introducing jitter.
Solution Approach 2:
The circuit dynamically adjusts the clock phase by selectively enabling or disabling specific delay paths based on detection of coincident rising edges. The control logic continuously monitors the alignment between clock and data signals and activates appropriate delay elements to maintain optimal timing without the complexity of a delay locked loop.
2Measurement precision
If a delay locked loop is used to retime clock signals, then the clock phase can be adjusted, but the system has high power consumption and constrictive operating parameters
Solution Approach 1:
Instead of continuously operating a delay locked loop with full power consumption, the circuit applies partial action by only activating specific delay elements when needed. The control logic enables individual inverter delay paths only when coincident rising edges are detected, reducing overall power consumption while maintaining the ability to achieve precise clock phase alignment when required.
3Productivity
If the rising edge of the clock signal is coincident with the rising edge of the data signals, then data can be transmitted, but it is difficult to process the data signals at the receiving location
Solution Approach 1:
The circuit performs preliminary action by detecting coincident rising edges between clock and data signals and proactively introducing delay to the clock signal before the data processing occurs. This preemptive timing adjustment ensures that the clock and data signals are properly aligned before they reach the processing logic, preventing processing difficulties rather than correcting them afterward.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively aligns clock and data signals, reducing jitter and power consumption compared to delay locked loops, while providing robust operation across various conditions, ensuring stable data processing even with coincident rising edges.
Implementation Method 1
The clock shifting circuit comprises a phase locked loop (PLL) with a reference input, a feedback input, and a PLL output... The PLL output is connected to the clock input of every D flip flop, and the Q-bar output of the last D flip flop in the series is buffered and connected to the feedback input of the PLL
Implementation Method 2
The clock shifting circuit comprises a phase locked loop (PLL) with a reference input, a feedback input, and a PLL output and a plurality of n D flip flops connected in series... The Q output of a D flip flop is connected to the D input of a subsequent D flip flop in the series
Data Source
AI summary
Method and system for aligning a clock signal to parallel data are described. According to one embodiment, a clock shifting circuit shifts an incoming clock signal relative to an incoming data signal, and a data clocking circuit uses the shifted clock signal to reclock the incoming data signal. The clock shifting circuit may comprise a phase locked loop (PLL) coupled with multiple D flip flops (DFFs) connected in series. Divisional combinatorial logic may be disposed between DFFs in the series. Data clocking circuits may comprise one DFF to reclock each incoming data bit, a pair of DFFs to reclock each incoming data bit, or other circuits such as true-complement blocks to serve as local oscillators to mixers. Multiple shifted clock signals may be produced, such as those shifted 60, 90, 120, 180, 240, and 270 degrees relative to the incoming clock signal.