PLL Clock Generation with Phase Interpolation for Accurate SSC
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Solution Overview
Problem
The existing semiconductor integrated circuit devices face challenges in generating spread spectrum clocks (SSC) due to the increased area requirements and reduced EMI attenuation caused by the use of low-pass filters in spread spectrum clock generators (SSCG), which limit high-frequency modulation and jitter performance.
Innovation Solution
A semiconductor integrated circuit device with a clock generation circuit that includes a PLL generating a first clock signal and phase-shifted second clock signals, a frequency divider, a frequency-divided clock selector, a phase interpolation circuit, and a control circuit to generate frequency modulation clocks, allowing for adjustable frequency division ratios and phase shifts without the need for a low-pass filter, thereby reducing circuit area and enhancing EMI attenuation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a low-pass filter is used in the spread spectrum clock generator to perform averaging processing, then the frequency division number can achieve non-integral values, but the filter band must be set sufficiently low which limits high-frequency modulation and increases filter size
Solution Approach 1:
The invention extracts and removes the low-pass filter from the spread spectrum clock generator circuit. Instead of using a filter to perform averaging processing, the patent uses a different architectural approach where the spread spectrum function is achieved through selective clock signal routing and phase adjustment, eliminating the need for a low-pass filter and its associated area constraints
Solution Approach 2:
The invention makes the clock generation circuit universal by enabling it to perform both integer and non-integer frequency division without requiring a low-pass filter. The circuit achieves spread spectrum functionality through a combination of frequency dividers with different division ratios and phase adjustment mechanisms, allowing the same circuit to handle various frequency division requirements
2Measurement precision
If a low-pass filter is used in the spread spectrum clock generator, then frequency averaging can be achieved, but the filter band limitation reduces EMI attenuation performance
Solution Approach 1:
The invention removes the low-pass filter from the circuit, eliminating the band limitation that constrained EMI attenuation performance. The spread spectrum clock generator achieves frequency averaging through alternative means that do not impose filter band constraints, thereby allowing effective high-frequency modulation for improved EMI attenuation
Solution Approach 2:
The invention changes the operational parameters of the clock generation circuit by using multiple frequency dividers with different division ratios (N and N-1) and combining their outputs through phase adjustment. This parameter-based approach achieves spread spectrum functionality without relying on filter band limitations, enabling better EMI attenuation across a wider frequency range
3Adaptability or versatility
If two types of clocks are generated using an SSCG and a PLL, then both spread spectrum and pure clock requirements are met, but the circuit area increases
Solution Approach 1:
The invention merges the spread spectrum clock generation and pure clock generation functions into a single integrated circuit. By using a unified architecture that can operate in different modes (spread spectrum mode and pure clock mode), the patent eliminates the need for separate SSCG and PLL circuits, thereby reducing the overall circuit area while maintaining the ability to generate both types of clocks
Solution Approach 2:
The invention creates a universal clock generation circuit that can perform both spread spectrum clock generation and pure clock generation functions. The circuit achieves this through configurable frequency dividers and phase adjustment mechanisms that can be controlled to produce either SSC or pure clock outputs, eliminating the need for separate dedicated circuits for each function
Data Source
AI summary
To generate a highly accurate SSC while reducing the circuit area of a clock generation circuit that generates a normal clock and an SSC. A clock signal output from a voltage controlled oscillator is frequency-divided by a frequency divider, and is output as a first frequency-divided clock to a selector. The frequency divider outputs a plurality of second frequency-divided clocks each shifted in phase by 1/m of a period based on a control signal of a control circuit. The selector selects two frequency-divided clocks having the closest phase shift from among the first and second frequency-divided clocks. Based on a weighting data signal output from the control circuit, a phase interpolation circuit phase-shifts the frequency-divided clock by a phase shift obtained by dividing the phase difference between the two frequency-divided clocks, and outputs the resultant clock as an output clock.