PLL Clocking With Open-Loop VCO Response to Supply Droop

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Solution Overview

Problem

The large slope of drain current (di/dt) in system on chip (SoC) logic causes the supply voltage to dip below the minimal working voltage (Vmin), leading to timing logic failure and data corruption.

Innovation Solution

A phase locked loop (PLL) circuit with a voltage controlled oscillator (VCO) and transconductance cell (Gm) that transitions to an open loop mode when the supply voltage approaches Vmin, reducing the frequency of operation proportionally to the voltage drop, and relocks to a reference clock when the voltage recovers, ensuring the SoC logic does not fail timing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the SoC logic processes large amount of data with large di/dt, then the processing capability is improved, but the supply voltage dips below Vmin causing timing logic failure

Engineering Contradiction:

Improvedata processing capabilityVSAvoidtiming logic operation

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the PLL continuously monitors the supply voltage and dynamically adjusts the clock frequency in response to voltage droops. The phase detector and voltage controlled oscillator form a closed-loop system that detects voltage changes and automatically compensates by reducing frequency, thereby preventing timing failures while maintaining high data processing capability during normal operation.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent employs dynamic frequency adjustment within the PLL circuit to adapt to changing supply voltage conditions. The clock frequency is not fixed but dynamically modulated based on real-time voltage monitoring, allowing the system to operate at high frequencies when voltage is stable and automatically reduce frequency when voltage droops occur due to large di/dt events during data processing.

Inventive Principle:

Principle #15Dynamics

2Reliability

If the clock frequency is reduced to prevent timing failures, then the reliability is improved, but the productivity decreases

Engineering Contradiction:

Improvetiming logic operationVSAvoiddata processing capability

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent utilizes periodic monitoring of supply voltage by the PLL circuit, where the phase detector continuously samples voltage levels and triggers frequency adjustments only when necessary. This periodic detection mechanism allows the system to maintain high clock frequencies during normal operation and only reduce frequency periodically when voltage droops are detected, thus minimizing productivity impact while ensuring reliability.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent changes the clock frequency parameter dynamically based on supply voltage conditions. Rather than operating at a fixed low frequency to ensure reliability, the system maintains high frequency operation during stable voltage conditions and only reduces frequency when voltage droops occur, optimizing the balance between productivity and reliability through parameter modulation.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20260005694A1Clocking system for a system on chip using pll

Publication Date: 2026.01.01 MICROSOFT TECHNOLOGY LICENSING LLC

AI summary

The described technology provides a device including a phase locked loop (PLL) circuit, the PLL circuit including a voltage controlled oscillator (VCO) and a phase detector, and a voltage supply and transconductance cell (Gm) configured to drain a current Iout from the VCO based on a sensed voltage (Vsup_sense) input into the Gm, wherein the Gm cell is configured to generate an open_loop signal based on the Iout drain from the VCO.