PLL Open-Loop Coarse Tuning for Fast Wide-Range Lock
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Solution Overview
Problem
Conventional phase locked loops (PLLs) in RF applications face significant delays in achieving phase and frequency lock due to their complexity, especially when required to cover wide tuning ranges.
Innovation Solution
A PLL with open loop coarse tuning logic, comprising a phase/frequency detector, charge pump, low pass filter, switch network, voltage controlled oscillator bank, divider, prescaler, counting circuit, and calibration logic, which allows for calibration of the VCO bank to select and trim the appropriate VCO within a predetermined range of the target frequency, enabling rapid phase and frequency lock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional PLL circuits are designed to cover wide tuning ranges, then the tuning range is improved, but the delay to achieve phase and frequency lock increases significantly
Solution Approach 1:
The VCO bank is divided into multiple individual VCOs, each covering a specific frequency sub-range. The calibration logic selectively enables only the VCOs necessary to cover the target frequency, rather than requiring all VCOs to be active simultaneously. This segmentation allows wide overall tuning range while reducing the active complexity and acquisition time for any given target frequency.
Solution Approach 2:
The calibration logic pre-determines which VCOs should be enabled based on the target frequency before the PLL acquisition process begins. By performing this selection in advance and configuring the appropriate VCOs beforehand, the system eliminates the time-consuming process of sequentially searching through all VCOs during lock acquisition, thus reducing the delay to achieve phase and frequency lock.
2Adaptability or versatility
If multiple VCOs are enabled to cover wide tuning ranges, then the tuning range is improved, but the complexity of the PLL circuit increases
Solution Approach 1:
The PLL circuit dynamically configures which VCOs are enabled based on the target frequency through the calibration logic. Rather than having a fixed configuration with all VCOs permanently active, the system adaptively enables only the necessary subset of VCOs for each target frequency, reducing the effective complexity while maintaining wide tuning range capability.
Solution Approach 2:
The calibration logic automatically determines and configures the appropriate VCOs based on the target frequency without requiring external intervention or complex control mechanisms. The system self-configures by enabling only the VCOs needed for the specific target frequency, thereby covering wide tuning ranges while minimizing circuit complexity.
3Speed
If all VCOs are kept active to ensure fast acquisition, then the acquisition speed is improved, but the power consumption and circuit complexity increase
Solution Approach 1:
Instead of uniformly activating all VCOs across the entire tuning range, the calibration logic applies local quality by enabling only the specific VCOs that correspond to the target frequency region. This localized activation ensures fast acquisition for the target frequency while avoiding the power consumption and complexity overhead of keeping all VCOs active.
Data Source
AI summary
In many types of wireless applications (like wireless modems), it is important that the phase locked loops (PLLs) be able to synthesize clock frequencies in a wide tuning range. Because of the complexity of many conventional PLLs (which were deigned to cover wide tuning ranges), there was often a significant delay to achieve phase and frequency lock. Here, an open loop calibration system is provided to coarse tune a PLL very rapidly. Generally, this calibration system employs binary searches to coarsely adjust a voltage controlled oscillator (VCO) from a VCO bank to within a predetermined range around a target frequency.