Two-Point Modulated PLL Compensation for Non-Uniform Clocks
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Solution Overview
Problem
Two-point modulated PLLs suffer from phase errors due to delay spreads between injection points, degrading error vector magnitude (EVM) and increasing out-of-band emission, particularly in non-uniform digital processing clocks.
Innovation Solution
A PLL circuit and method that includes a controlled oscillator, a first and second input path for phase and frequency control, and a non-uniform clock compensation circuit to recursively calculate compensation values, correcting phase errors in both direct and phase prediction paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two-point modulation is used to overcome bandwidth limitations, then wideband frequency or phase modulation is enabled, but delay spread between injection points degrades EVM and increases out-of-band emission
Solution Approach 1:
The patent applies preliminary action by predicting the phase of the controlled oscillator in advance using a phase predictor. The predicted phase value is calculated before the actual phase measurement, allowing the system to compensate for delay spread effects proactively. This prediction mechanism enables the receiver to prepare compensation values ahead of time, mitigating the EVM degradation caused by delay spread between the two injection points.
Solution Approach 2:
The patent implements feedback through a phase error detector that continuously monitors the phase difference between the predicted phase and the actual phase of the controlled oscillator. This feedback loop allows the system to detect phase errors caused by delay spread and generate correction signals that are fed back to compensate for these errors, thereby improving EVM while maintaining wideband modulation capability.
2Ease of operation
If non-uniform digital processing clock is used, then processing flexibility is improved, but phase errors increase due to delay spread
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the phase prediction based on the varying clock periods in non-uniform digital processing. The system modifies the phase accumulation calculations to account for changing clock frequencies, allowing flexible processing while compensating for the phase accuracy degradation that would otherwise result from non-uniform timing.
3Measurement precision
If delay spread compensation is implemented, then EVM is improved, but device complexity increases
Solution Approach 1:
The patent introduces an intermediary phase predictor component that mediates between the two injection points and the phase detector. This intermediary calculates predicted phase values that account for delay spread, effectively isolating the rest of the system from the timing discrepancies. By placing this computational intermediary in the signal path, the system achieves EVM improvement without requiring complex hardware modifications to the oscillator or injection circuitry.
Data Source
AI summary
A PLL circuit for generating a modulated carrier signal includes a digitally controlled oscillator (DCO) to generate the modulated signal. The PLL circuit receives a desired phase change as a modulation signal at each cycle of a non-uniform clock, derived from the a DCO output and a uniform reference clock. This phase change adjusts the DCO's frequency. The circuit also receives a frequency control word, representing the ratio of the desired carrier frequency to the reference clock frequency. The phase change and frequency control word are accumulated to predict the DCO's output phase. A non-uniform clock compensation circuit calculates a compensation value for the phase change. A phase detector estimates the error between the predicted phase and the time offset between the reference clock and DCO output, generating a control signal for the DCO based on this error.