PLL Counter Synchronization for Aligned Multi-PLL Output Clocks
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Solution Overview
Problem
Existing solutions for phase-locked loops (PLLs) fail to synchronize and align the phases of output clock signals across multiple PLLs, which is crucial for systems requiring coordinated clock signals.
Innovation Solution
An apparatus and method that utilize a local counter, comparator, and multiplexor within each PLL to synchronize output clock signals by comparing counts with a predetermined value and incrementing them to align with adjacent PLLs, enabling the output clock divider when a predetermined count is reached, allowing for configurable synchronization groups and rearrangement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple PLLs operate independently with the same reference clock and division ratios, then each PLL can function autonomously, but the output clock signals remain unsynchronized with random phase relationships
Solution Approach 1:
A dedicated synchronization circuit acts as an intermediary between multiple PLLs, using cross-PLL sampling to detect phase differences and generate correction signals. This mediator approach enables phase synchronization without requiring complex inter-PLL communication or coordination protocols.
Solution Approach 2:
The synchronization circuit implements feedback by continuously sampling output clock signals from adjacent PLLs, comparing their phases, and generating phase adjustment signals that feed back to the VCOs. This closed-loop feedback mechanism dynamically maintains phase alignment despite variations in operating conditions.
2Manufacturing precision
If phase synchronization circuits are added to align output clock signals across PLLs, then phase alignment is achieved, but the system complexity and circuit overhead increase
Solution Approach 1:
The synchronization functionality is merged with the existing PLL structure by utilizing the output clock divider and phase detector components already present in each PLL. The cross-PLL sampling and phase comparison functions are integrated into the existing feedback path, eliminating the need for completely separate synchronization circuits.
Solution Approach 2:
The phase detector and loop filter components within each PLL serve dual functions: maintaining the PLL's internal frequency locking and simultaneously enabling cross-PLL phase synchronization. This multi-functionality reduces the need for additional dedicated synchronization hardware.
3Reliability
If cross-PLL sampling and phase comparison are implemented, then output clock signals can be synchronized, but the system requires additional sampling circuits and phase detection mechanisms
Solution Approach 1:
Each PLL uses its own existing phase detector and feedback mechanism to perform the phase comparison function for synchronization. The PLL's natural phase detection capability is leveraged to detect phase differences with adjacent PLLs, eliminating the need for separate phase comparison circuits.
Solution Approach 2:
The output clock divider serves as an intermediary that makes the high-frequency VCO output suitable for sampling and phase comparison. By dividing down the frequency, the sampling circuits can operate at lower frequencies with standard digital logic, reducing the complexity of high-speed sampling requirements.
Data Source
AI summary
An apparatus and a method for synchronizing output clock signals across a plurality of phase-locked loops (PLLs). The apparatus coupled within each PLL comprises: a local counter configured to provide a count when receiving a reference clock signal; a comparator configured to compare the count from the local counter with a predetermined or preconfigured value; wherein a multiplexor connected to the local counter and counters of adjacent PLLs, configured to select the count from the local counter or a count from the counters of the adjacent PLLs; wherein the selected count from the multiplexor is incremented and directed to the local counter; wherein an output clock divider enable is asserted to the PLL to start an output clock divider to generate the output clock signal when the count from the local counter reaches the predetermined or preconfigured value.