PLL Feedback Delay Layout for Power-Noise Jitter Suppression
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Solution Overview
Problem
Conventional PLL circuits experience increased jitter due to overlapping power-supply noise and phase comparison timing, which destabilizes the output signal, particularly in semiconductor IC devices with both analog and digital circuits.
Innovation Solution
A phase-locked loop (PLL) circuit design that includes a phase comparator, an oscillator, a feedback loop, and a delay circuit positioned outside the feedback loop, where the delay circuit automatically adjusts its delay time based on the output signal's frequency, ensuring the power-supply noise does not overlap with the phase comparison timing, thereby reducing jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digital circuits operate synchronously with the PLL output signal, then circuit operation efficiency is improved, but power-supply noise overlaps with phase comparison timing causing increased jitter
Solution Approach 1:
The patent segments the feedback path by inserting a delay circuit between the voltage-controlled oscillator and the phase comparator. This segmentation allows the digital circuit to operate synchronously with the PLL output signal while the delayed feedback signal prevents power-supply noise from overlapping with the phase comparison timing, thus resolving the contradiction between operational efficiency and signal stability.
Solution Approach 2:
The delay circuit introduces a preliminary time delay to the feedback signal before it reaches the phase comparator. This preliminary action ensures that the phase comparison occurs at a timing point free from power-supply noise generated by synchronous digital circuit operation, thereby maintaining signal stability without sacrificing circuit operation efficiency.
2Reliability
If delay circuit is added to separate noise from phase comparison timing, then jitter is reduced, but circuit complexity increases
Solution Approach 1:
The patent introduces a delay circuit as an intermediary element between the voltage-controlled oscillator and the phase comparator. This intermediary component effectively separates the power-supply noise from the phase comparison timing, reducing jitter while maintaining relatively simple circuit architecture. The delay circuit acts as a mediator that resolves the timing conflict without requiring fundamental redesign of the PLL structure.
3Reliability
If phase comparison timing is adjusted to avoid noise, then jitter is reduced, but lock-up time increases
Solution Approach 1:
The patent replaces the conventional approach of adjusting phase comparison timing through complex feedback control mechanisms with a simpler time-domain separation approach. By using a delay circuit to physically separate the noise generation timing from the phase comparison timing, the system achieves jitter reduction without significantly increasing lock-up time, as the delay is fixed and does not require dynamic adjustment during acquisition.
Data Source
AI summary
A phase locked loop (PLL) circuit including a phase comparator for comparing a phase of a reference signal with a phase of a feedback signal, an oscillator for outputting an output signal at a frequency in accordance with an output of the phase comparator, a feedback loop for returning the output signal of the oscillator and supplying the output signal as the feedback signal, and a delay circuit for delaying the phase of the output signal output from the oscillator to a load circuit, wherein the delay circuit is provided outside the feedback loop.