PLL Phase Frequency Detector and Charge Pump for Fast Locking
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Solution Overview
Problem
Phase lock loop (PLL) circuits face challenges in reducing locking time without increasing noise or frequency breadth limitations, and existing solutions require significant circuit area to boost charge pump gain.
Innovation Solution
The implementation of a phase frequency detector system with flip-flops, delay elements, and gated core circuits to provide delayed pulses, along with a programmable feedback divider and charge pump, enhances gain without increasing circuit footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If charge pump gain is boosted to reduce locking time, then locking time is reduced, but circuit area increases significantly
Solution Approach 1:
The feedback divider is segmented into multiple stages (first feedback divider and second feedback divider) that can be independently controlled. This segmentation allows the system to achieve fast locking by activating only the necessary divider stages during acquisition, reducing the overall circuit area while maintaining fast-locking capability.
Solution Approach 2:
The system dynamically switches between different feedback divider configurations based on operating mode. A first feedback divider with lower division ratio is used during acquisition for fast locking, while a second feedback divider with higher division ratio is used during normal operation. This dynamic reconfiguration reduces the required charge pump gain and circuit area while maintaining fast-locking performance.
2Loss of time
If charge pump current is increased to reduce locking time, then locking time is reduced, but noise increases
Solution Approach 1:
The system dynamically adjusts the feedback division ratio based on operating mode. During acquisition, a lower division ratio is used which effectively increases the charge pump gain without actually increasing the physical current, thus reducing locking time without introducing excess noise. During normal operation, the higher division ratio restores noise performance.
Solution Approach 2:
The system changes the feedback division ratio parameter between acquisition and normal operation modes. This parameter change effectively modulates the charge pump gain during acquisition to achieve fast locking, while restoring the original gain during normal operation to maintain low noise performance.
3Speed
If feedback divider ratio is adjusted to extend bandwidth, then bandwidth is extended, but locking time increases
Solution Approach 1:
The feedback divider ratio is dynamically adjusted based on operating mode. During acquisition, the divider ratio is set to extend bandwidth for fast locking. During normal operation, the divider ratio is adjusted to optimize phase tracking performance. This dynamic adjustment allows bandwidth extension only when needed for fast locking, preventing locking time increase during normal operation.
Data Source
AI summary
The present invention provides for a solution to reduce locking time with satisfactory performance without the need for significant footprint area for the phase lock loop (PLL) circuits by boosting phase frequency detector (PFD) and charge pump (CP) gains through various circuitry configurations that employ one or more flip-flops, delay elements and advanced circuitry techniques.