Hybrid-Calibrated PLL Circuit for Fast Locking and Low Phase Noise
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Solution Overview
Problem
Existing phase-locked loop (PLL) circuits face challenges in achieving low settling time while maintaining low phase noise, particularly in Bluetooth applications, due to the need for capacitor bank calibration and limited bandwidth.
Innovation Solution
A hybrid loop calibration scheme combined with adaptively updated lookup tables is employed, utilizing open-loop and closed-loop calibration phases to quickly settle PLL parameters, and a turbo locking scheme with adjustable loop bandwidths to enhance frequency-hopping performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If capacitor bank calibration is performed to cover target frequency, then frequency coverage is improved, but settling time increases significantly
Solution Approach 1:
The patent pre-calibrates the capacitor bank to store calibration data for multiple target frequencies in advance. This preliminary calibration results are stored and reused during frequency hopping, eliminating the need for real-time calibration and thus reducing settling time while maintaining comprehensive frequency coverage.
Solution Approach 2:
The patent prepares calibration data for various frequency scenarios in advance and stores it in lookup tables. This beforehand preparation cushions against the time penalty that would otherwise be incurred during actual frequency transitions, allowing rapid switching without recalibration.
2Object-affected harmful factors
If small bandwidth is used to meet low phase noise requirement, then phase noise is reduced, but settling time becomes even longer
Solution Approach 1:
The patent dynamically adjusts the PLL bandwidth during different phases of operation. During frequency acquisition and hopping, a larger bandwidth is used to enable fast settling. Once locked, the bandwidth is reduced to minimize phase noise. This dynamic adjustment resolves the contradiction between fast settling and low phase noise.
Solution Approach 2:
The patent employs periodic bandwidth adjustment where the PLL operates in different bandwidth modes at different times. The system switches between wide-bandwidth mode for frequency acquisition and narrow-bandwidth mode for steady-state operation, achieving both fast settling and low phase noise at appropriate moments.
3Reliability
If frequency hopping is implemented to overcome interference, then communication reliability is improved, but PLL settling time must be completed within each hopping interval
Solution Approach 1:
The patent performs preliminary calibration and stores the results in advance for all possible frequency channels. When frequency hopping is required, the pre-computed calibration data is immediately retrieved from lookup tables without requiring real-time computation, enabling the PLL to settle within the tight hopping interval while maintaining communication reliability.
Solution Approach 2:
The patent creates and stores copies of calibration data for multiple frequency channels in advance. During frequency hopping, instead of performing full calibration, the system copies and applies the pre-stored calibration parameters from the appropriate lookup table entry, enabling rapid frequency switching while maintaining accuracy.
Data Source
AI summary
A phase-locked loop (PLL) circuit includes a PLL core circuit, at least one lookup table, and a control circuit. The PLL core circuit generates an output clock under an open-loop calibration phase and a closed-loop calibration phase. The control circuit loads PLL parameters that are derived from the at least one lookup table to the PLL core circuit, performs open-loop calibration upon a first part of the PLL parameters under the open-loop calibration phase of the PLL core circuit, and performs closed-loop calibration upon a second part of the PLL parameters under the closed-loop calibration phase of the PLL core circuit.