PLL Feedback Divider Using Ripple Counter for Faster Lock

Solution Overview

Problem

Digital PLLs face limitations in phase detection range, leading to slow locking or failure, necessitating additional circuitry and increased power consumption for fast lock techniques.

Innovation Solution

Combining the functionality of an accumulator with a feedback divider to provide coarse phase and frequency information, using a ripple counter to adjust the oscillator control signal, thereby eliminating the need for extra circuitry and enhancing lock speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If an accumulator is added to provide coarse phase and frequency information for fast lock, then lock speed is improved, but device complexity and power consumption increase

Engineering Contradiction:

Improvelock timeVSAvoidcircuit complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent combines the accumulator functionality with the feedback divider by using the feedback divider to generate both the feedback clock signal and coarse phase/frequency information. The feedback divider is sampled to supply frequency error information and second phase error information, merging what would traditionally be separate components into one unified structure, thereby achieving fast lock without increasing device complexity

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The feedback divider is designed to perform multiple functions: generating the feedback clock signal, providing coarse phase error information, and supplying frequency error information when sampled. This multi-functional design eliminates the need for a dedicated accumulator circuit while maintaining fast lock capability

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Loss of time

If an accumulator is added to provide coarse phase and frequency information for fast lock, then lock speed is improved, but power consumption increases

Engineering Contradiction:

Improvelock timeVSAvoidpower consumption

Core Design Contradiction:

Loss of timeVSUse of energy by stationary object

Solution Approach 1:

The patent combines the accumulator functionality with the feedback divider by using the feedback divider to generate both the feedback clock signal and coarse phase/frequency information. The feedback divider is sampled to supply frequency error information and second phase error information, merging what would traditionally be separate components into one unified structure, thereby achieving fast lock without increasing device complexity

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The feedback divider is designed to perform multiple functions: generating the feedback clock signal, providing coarse phase error information, and supplying frequency error information when sampled. This multi-functional design eliminates the need for a dedicated accumulator circuit while maintaining fast lock capability

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Device complexity

If a conventional phase detector is used, then circuit simplicity is maintained, but phase detection range is limited leading to slow locking

Engineering Contradiction:

Improvecircuit complexityVSAvoidlock time

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The patent implements a feedback mechanism where the feedback divider is sampled to generate frequency error information and second phase error information. This sampled feedback provides coarse phase and frequency information that extends the effective detection range and enables faster locking without complicating the basic circuit structure

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The feedback divider is designed to perform multiple functions: generating the feedback clock signal, providing coarse phase error information, and supplying frequency error information when sampled. This multi-functional design eliminates the need for a dedicated accumulator circuit while maintaining fast lock capability

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12483251B2Feedback divider in a PLL used as a phase/frequency detector

Publication Date: 2025.11.25 SILICON LABORATORIES INC

AI summary

A phase-locked loop (PLL) uses a feedback divider to provide phase and frequency information for faster lock. The PLL includes a time to digital converter that generates first phase information indicative of a phase difference between a reference clock and a feedback clock. A digital filter receives the first phase information and generates an oscillator control signal used by an oscillator to generate an oscillator output. A feedback divider uses a ripple counter to divide the oscillator output to generate the feedback clock. One sample of the ripple counter provides second phase information and two samples of the ripple counter provide frequency information, which are used to generate the oscillator control signal. The one sample of the ripple counter is compared to an expected value when the PLL is locked to generate second phase information and a difference between the two samples is used to generate the frequency information.