PLL Loop Filter Switching Layout for Parasitic Noise Isolation

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Solution Overview

Problem

Parasitic capacitance on the control input of a current source device in phase-locked loops introduces noise into the power supply, affecting the loop filter's signal and current to the current controlled oscillator, leading to instability in the phase-locked loop.

Innovation Solution

A loop filter architecture with binary-weighted capacitors and switches is designed to minimize parasitic capacitance by using switches with controlled resistance, reducing noise injection into the gate-to-source voltage of the current source device, thereby stabilizing the oscillator frequency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If switches are connected directly to the control input of the current source device, then the loop filter signal can be transmitted, but parasitic capacitance introduces noise into the power supply affecting stability

Engineering Contradiction:
Improvephase-locked loop stabilityVSAvoidparasitic capacitance noise
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The switch network is divided into two separate groups: first plurality of switches connected to the charge pump and binary-weighted capacitors but not to the control input, and second plurality of switches connected to the control input. This segmentation isolates the parasitic capacitance of the first switches from the control input, preventing noise injection while maintaining signal transmission capability through the second switches.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The binary-weighted capacitors serve as an intermediary element between the first plurality of switches and the control input. The capacitors are charged through the first switches from the charge pump, then discharged through the second switches to the control input. This intermediary arrangement allows signal transmission while isolating the noisy switch nodes from the sensitive control input.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If binary-weighted capacitors are used with switch networks, then loop filter functionality is achieved, but parasitic capacitance on control input increases noise

Engineering Contradiction:
Improveloop filter signal controlVSAvoidnoise injection to current source
Core Design Contradiction:
Ease of operationVSObject-generated harmful factors

Solution Approach 1:

The switch network is divided into two separate groups: first plurality of switches connected to the charge pump and binary-weighted capacitors but not to the control input, and second plurality of switches connected to the control input. This segmentation isolates the parasitic capacitance of the first switches from the control input, preventing noise injection while maintaining signal transmission capability through the second switches.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The control input connection is extracted from the first plurality of switches and assigned only to the second plurality of switches. By taking out the direct connection between the first switches and control input, the parasitic capacitance associated with the first switches is removed from the noise-sensitive path, eliminating the noise injection problem while preserving the loop filter's control functionality.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentEP3900191B1Loop filter for a phase-locked loop
Publication Date: 2025.07.09 TEXAS INSTRUMENTS INC
  • EP3900191B1 patent drawingFigure 1~3
  • EP3900191B1 patent drawingFigure 4

AI summary

A circuit includes a first filter (402), a plurality of binary -weighted capacitors (C1, C2, Cn), and a current source device (Ml). The circuit also includes a first plurality of switches (SW3). Each of the first plurality of switches (SW3) is connected to a separate capacitor of the plurality of binary- weighted capacitors (C1, C2, Cn). The first plurality of switches (SW3) are connected together, and the first plurality of switches (C1, C2, Cn) are not connected to the first filter. A second plurality of switches (SW2) is also included, and each of the second plurality of switches (SW2) is connected to a separate capacitor of the plurality of binary-weighted capacitors (C1, C2, Cn) and to the first filter (402) and to a control input of the current source device (M1). The first plurality of switches (SW3) is not connected to the control input.