PLL Frequency Compensation Circuit for PVT Lock Stability

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Solution Overview

Problem

Phase-locked loops (PLLs) are susceptible to frequency shifts due to process, voltage, and temperature variations (PVT), leading to unlocking and loss of synchronization with reference signals.

Innovation Solution

A frequency compensation circuit within the PLL that adjusts a control current to stabilize the output frequency by detecting deviations in control voltage, using a voltage monitor, frequency selector, and current bias circuits to maintain synchronization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional PLL circuit is used, then the circuit structure is simple, but the output frequency shifts due to PVT variations causing the PLL to unlock

Engineering Contradiction:
ImprovePLL locking stabilityVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism where the control voltage from the phase-locked loop is monitored and fed back to the frequency compensation circuit. This feedback loop enables real-time detection of frequency deviations and automatic compensation by adjusting the control current, thereby maintaining stable locking despite PVT variations.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent dynamically changes the control current parameter based on the control voltage level. When the control voltage exceeds a threshold, indicating frequency deviation, the frequency compensation circuit adjusts the control current to compensate for the frequency shift, thus maintaining the output frequency at the desired target frequency.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If frequency compensation is added to compensate for PVT variations, then the PLL locking stability is improved, but the circuit complexity increases

Engineering Contradiction:
Improvefrequency stabilityVSAvoidcircuit components
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The frequency compensation circuit is segmented into distinct functional modules: a voltage monitoring unit that detects control voltage levels, a frequency selection unit that determines compensation magnitude, and a current bias unit that generates the compensating control current. This segmentation allows for targeted frequency compensation without requiring complete circuit redesign.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The frequency compensation circuit performs preliminary action by proactively adjusting the control current before the PLL completely unlocks. By monitoring the control voltage and detecting early signs of frequency deviation, the circuit applies compensatory current adjustments to prevent unlocking, rather than attempting to recover after loss of lock.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12500590B2Phase-locked loop circuit
Publication Date: 2025.12.16 MEDIATEK SINGAPORE PTE LTD
  • US12500590B2 patent drawing
  • US12500590B2 patent drawing
  • US12500590B2 patent drawing

AI summary

A PLL circuit generates an output signal having an output frequency and includes a voltage-to-current conversion circuit, a frequency compensation circuit, and an ICO. The voltage-to-current conversion circuit is configured to generate a first control current according to a control voltage, wherein the control voltage is generated according to a reference signal and a feedback signal derived from the output signal. The frequency compensation circuit is configured to generate a second control current according to the control voltage. The ICO generates the output signal according to an oscillation current, wherein the oscillation current is a sum of the first control current and the second control current. In response to the frequency compensation circuit detecting that the control voltage is out of a predetermined range, the second control current is controlled to be negatively correlated with the output frequency.