PLL Two-Point Frequency Search for Fast Lock Acquisition
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Solution Overview
Problem
Phase-locked loop (PLL) circuits face long settling times during system startup, which can exceed 180 microseconds, limiting system initialization due to the time required to synchronize and stabilize the output clock signal with the input reference signal.
Innovation Solution
A hybrid digital and analog control method is implemented in the PLL, utilizing a two-point frequency search for open-loop digital control and closed-loop analog control to converge the output frequency to a programmed value within a tight frequency variance, reducing settling time to approximately 3 microseconds or less.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional closed-loop analog control is used in PLL, then frequency accuracy is maintained, but settling time becomes excessively long (exceeding 180 microseconds)
Solution Approach 1:
The patent applies preliminary action by performing open-loop digital frequency control before closed-loop analog control. The digital controller pre-adjusts the VCO frequency based on measured frequency error, bringing the PLL closer to lock before engaging the analog control loop, thereby reducing the settling time required for frequency acquisition
Solution Approach 2:
The patent changes control parameters by switching between digital control (coarse frequency adjustment) and analog control (fine frequency adjustment). The digital controller modifies the VCO control voltage in discrete steps based on frequency measurements, while the analog controller provides continuous fine-tuning, combining both approaches to achieve fast settling with high accuracy
2Loss of time
If open-loop digital control is used to reduce settling time, then settling time decreases, but frequency accuracy may be compromised
Solution Approach 1:
The patent segments the frequency control process into two distinct phases: open-loop digital control for fast frequency acquisition and closed-loop analog control for precision frequency stabilization. Each control mode operates in a specific sequence, with digital control handling coarse adjustments and analog control handling fine adjustments, thereby achieving both fast settling and high accuracy
Solution Approach 2:
The patent implements feedback by measuring the actual VCO frequency using a frequency counter, comparing it with the target frequency, and using the frequency error to adjust the VCO control voltage. The feedback loop continuously monitors and corrects frequency deviations, ensuring both fast settling time and high frequency accuracy through iterative refinement
Data Source
AI summary
In an example, a phase-locked loop (PLL) circuit includes an oscillator, a frequency search circuit, and an analog control loop. The oscillator is configured to provide a clock signal. The frequency search circuit is configured to measure a first frequency of the clock signal for a first clock control signal, measure a second frequency of a second signal for a second clock control signal, and determine, based on the first frequency, the second frequency, the first clock control signal, and the second clock control signal, a third clock control signal corresponding to a programmed frequency, the third clock control signal for causing the clock signal to have a frequency based on the programmed frequency. The analog control loop is configured to control the oscillator to cause the frequency to converge to the programmed frequency.