PLL Holdover Switching With Divider Phase Alignment
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Solution Overview
Problem
Existing phase locked loops (PLLs) experience disruptions and loss of lock during reference clock switching due to phase misalignment between redundant oscillators, leading to potential system crashes.
Innovation Solution
Implementing a holdover mode in the PLL that decouples the output from the oscillators, adjusts the divisor using a multi-mode divider to align the feedback clock with the new reference, and maintains a constant output frequency during the transition, ensuring minimal disruption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant reference clocks are used to improve reliability, then system reliability improves, but phase misalignment between oscillators causes disruptions during switching
Solution Approach 1:
The patent performs phase alignment in advance during a holdover mode before the actual oscillator switching occurs. The PLL is temporarily decoupled from the output, the new reference oscillator is activated and aligned in phase with the current feedback clock, and only then is the switching completed. This preliminary alignment action prevents phase offset disruptions during operational switching.
Solution Approach 2:
The patent introduces a holdover mode as an intermediary state between normal operation and oscillator switching. During this intermediate state, the PLL output is decoupled and a temporary feedback path is established that allows phase alignment without affecting the main output signal. This intermediary mechanism enables safe transitions between oscillators.
2Speed
If oscillators are switched directly without alignment, then switching speed is fast, but phase offset causes PLL to lose lock and stop functioning
Solution Approach 1:
Phase alignment is performed in advance during holdover mode before the final switching to the new oscillator. This ensures the PLL remains locked and functional throughout the transition, preventing loss of lock while maintaining relatively fast switching through efficient alignment procedures.
3Reliability
If phase alignment circuitry is added to maintain alignment, then hitless switching is achieved, but device complexity increases
Solution Approach 1:
The patent employs a dynamic multi-mode divider that can operate in different modes (normal operation mode and holdover alignment mode). This dynamic component allows the system to switch between operational states without requiring separate dedicated alignment circuitry, thereby achieving hitless switching while minimizing additional complexity.
Solution Approach 2:
The holdover mode mechanism serves multiple functions: it enables phase alignment, facilitates safe oscillator switching, and maintains PLL stability. By making this mechanism multi-functional, the patent reduces the need for separate dedicated circuits for each function, thereby controlling overall device complexity while achieving reliable hitless switching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Achieves hitless or near hitless reference clock switching by aligning feedback and reference clocks, reducing disturbances and maintaining PLL stability during oscillator transitions.
Implementation Method 1
a crystal oscillator circuit 110 including a piezo-electric crystal 114
Data Source
Figure 1~2
Figure 3~5
Figure 6~7
AI summary
A phase-locked loop (PLL) performs hitless switching from a first reference clock (refl) to a second reference clock (ref2) by entering holdover mode (418), and aligning the feedback clock (fbclk) to the second reference clock while in holdover mode. The alignment is performed by adjusting a divisor input (D) for the multi-mode divider (128) that divides the output clock frequency (PLLout) to generate the feedback clock. Other features are also provided.