PLL Loop Division Factor Adjustment for Jittery Input Ticks
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Solution Overview
Problem
Existing phase locked loops (PLLs) struggle to maintain correspondence between input and output data due to jitter in packet arrival times, potentially causing buffer overflow in automotive Ethernet systems.
Innovation Solution
A circuit and method to adjust the loop division factor (LDF) of a PLL based on a moving average of jitter, updating the LDF more frequently for static jitter and less frequently for variable jitter to compensate for timing deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the local clock frequency is kept very steady to ensure accurate serialization, then the correspondence between input packets and output bits is maintained, but jitter in packet tick frequency causes buffer overflow
Solution Approach 1:
The patent applies dynamics by making the loop division factor adjustable and variable rather than fixed. The LDF is dynamically modified based on detected jitter characteristics, allowing the PLL to adapt its division ratio in response to input frequency variations. This enables the system to maintain stable clock output while compensating for jitter-induced timing deviations, thereby preventing buffer overflow.
Solution Approach 2:
The patent changes the parameter of the loop division factor based on detected jitter. By measuring the deviation between expected and actual packet arrival times, the system calculates an adjusted LDF that compensates for jitter. This parameter change allows the PLL to maintain accurate serialization timing even when input packets arrive with jitter, resolving the contradiction between clock stability and overflow prevention.
2Measurement precision
If the loop division factor is adjusted frequently to compensate for variable jitter, then timing accuracy is improved, but system complexity increases
Solution Approach 1:
The patent implements feedback by continuously monitoring the actual arrival times of packet ticks and comparing them against expected timing. Based on this feedback, the system calculates jitter and adjusts the loop division factor accordingly. The feedback mechanism includes determining whether jitter is static or variable and adapting the LDF update frequency相应地, which improves timing accuracy without requiring excessively complex adjustment mechanisms.
Solution Approach 2:
The system dynamically adapts the frequency of LDF adjustments based on jitter characteristics. For static jitter, the LDF is updated less frequently, while for variable jitter, updates occur more often. This dynamic approach optimizes timing accuracy while managing system complexity by avoiding unnecessary frequent adjustments when jitter is stable.
3Reliability
If the loop division factor is adjusted to compensate for jitter, then buffer overflow is prevented, but the correspondence between input and output data may be disrupted
Solution Approach 1:
The patent carefully adjusts the loop division factor based on calculated jitter values to compensate for timing deviations without disrupting the fundamental input-output correspondence. By modifying the LDF in proportion to the detected jitter, the system prevents buffer overflow while maintaining accurate serialization. The adjustment is calibrated to correct timing errors without creating new correspondence issues.
Solution Approach 2:
The feedback mechanism continuously monitors both the effectiveness of LDF adjustments and the maintenance of input-output correspondence. By comparing expected versus actual timing after adjustments, the system can fine-tune the LDF modification strategy to prevent overflow while preserving data correspondence, resolving the contradiction between these two requirements.
Data Source
AI summary
In accordance with various embodiments of the present disclosure, a circuit to adjust a loop division factor (LDF) of a phase locked loop (PLL) is provided. In some embodiments, the circuit comprises processing circuitry configured to (1) determine an amount of jitter of a received input frequency comprising a plurality of input ticks, the amount of jitter being an amount of variation between an expected receipt of each of the plurality of input ticks and an actual receipt thereof, (2) determine a moving average of the determined amount of jitter, (3) determine an adjusted LDF based on the determined moving average of the determined amount of jitter, and (4) output the adjusted LDF to a PLL.