PLL Calibration Using Jitter Injection for Stable Loop Bandwidth
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Solution Overview
Problem
The loop bandwidth of phase-locked loops (PLL) in communication systems is challenging to calibrate due to variability caused by external environments, manufacturing errors, or voltage changes, making it difficult to maintain within a specific range.
Innovation Solution
A phase-locked loop circuit calibration method that involves generating a jitter signal and using it to modify an incoming signal from a host system, allowing the PLL to perform a phase-lock operation and detect the resulting signal to calibrate electronic parameters such as loop bandwidth and jitter peaking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the loop bandwidth of the PLL is adjusted to adapt to external environment changes, manufacturing errors, or voltage changes, then the adaptability of the PLL is improved, but the difficulty of calibrating the loop bandwidth within a specific range increases
Solution Approach 1:
The patent applies parameter changes by adjusting the loop bandwidth of the PLL through controlled jitter signal injection. By varying the jitter amplitude and frequency parameters in a systematic calibration process, the loop bandwidth can be tuned to specific target values, resolving the contradiction between adaptability and calibration difficulty
Solution Approach 2:
The patent implements feedback mechanisms where the PLL output signal is monitored and compared against reference signals during calibration. This feedback loop enables automatic adjustment of loop bandwidth parameters, reducing manual calibration complexity while maintaining adaptability to environmental changes
2Measurement precision
If jitter signal is injected to calibrate the PLL, then the measurement precision of loop bandwidth is improved, but the device complexity increases due to additional jitter generation and detection circuits
Solution Approach 1:
The patent achieves multi-functionality by designing the jitter generation circuit to serve dual purposes: it generates calibration signals for loop bandwidth measurement and also functions as part of the normal PLL operation. This reduces overall device complexity while maintaining high measurement precision
Solution Approach 2:
The calibration system performs self-service by using internally generated jitter signals and automatic detection mechanisms. The PLL circuit itself provides the necessary signals for calibration through its normal operation, eliminating the need for external complex calibration equipment
Data Source
AI summary
A phase-locked loop circuit calibration method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: receiving a first signal from a host system; generating a jitter signal by the memory storage device; generating a second signal according to the first signal and the jitter signal; performing a phase-lock operation on the second signal to generate a third signal by a phase-locked loop circuit; and detecting the third signal to calibrate an electronic parameter of the phase-locked loop circuit.