On-Chip PLL Jitter Measurement Using Phase-to-Voltage Conversion
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Solution Overview
Problem
Existing methods for screening phase-locked loop (PLL) parts for jitter exceed target specifications are time-consuming and costly, and digital signal processing algorithms provide insufficient resolution for accurate jitter measurement.
Innovation Solution
A jitter measuring circuit integrated on-chip with a PLL, utilizing existing components like an analog-to-digital converter, generates analog jitter measurements that are digitized and processed to estimate jitter, allowing high-resolution screening.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If digital signal processing algorithms are used for jitter measurement, then device complexity is reduced, but measurement precision becomes insufficient
Solution Approach 1:
The jitter measurement function is segmented into two parts: an analog front-end that performs high-precision phase-to-voltage conversion, and a digital back-end that processes the converted signals. This segmentation allows the analog portion to handle precision requirements while the digital portion manages complexity.
Solution Approach 2:
An intermediary phase-to-voltage conversion circuit is introduced between the clock signals and the digital processing system. This intermediary converts the hard-to-measure phase differences into easily measurable voltage differences, enabling high-precision measurement without requiring complex digital algorithms.
2Measurement precision
If existing screening methods are used to identify parts exceeding jitter specifications, then measurement accuracy is achieved, but productivity decreases due to time-consuming processes
Solution Approach 1:
The PLL circuit is equipped with an integrated self-test capability that allows it to measure its own output clock signal's jitter. This eliminates the need for external expensive testing equipment and time-consuming manual measurement processes, enabling fast automated screening while maintaining high measurement accuracy.
Solution Approach 2:
The jitter measurement circuit is designed to be universally applicable to any PLL circuit, allowing the same circuit architecture to measure jitter across different PLL implementations. This multi-functionality enables standardized testing procedures that improve productivity without sacrificing measurement precision.
3Device complexity
If time-stamper resolution is used for jitter measurement, then device complexity is minimized, but measurement precision is limited by the time-stamper resolution
Solution Approach 1:
The measurement parameter is changed from direct time/phase measurement (limited by time-stamper resolution) to voltage measurement. By converting phase differences into voltage differences through the phase-to-voltage conversion circuit, the system achieves higher measurement precision since voltage can be measured with greater resolution than time intervals.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces test time and cost by avoiding expensive equipment, achieving high-resolution jitter measurement with accuracy not limited by time-stamper resolution, suitable for both on-chip and production test environments.
Implementation Method 1
a capacitor electrically connected between an output node and a first reference voltage
Data Source
AI summary
Apparatus and methods for jitter testing of clock signals are disclosed. In certain embodiments, a jitter measuring circuit is used to obtain jitter measurements of a PLL's clock signal in an analog domain. For example, the analog jitter measurements can be generated by discharging a capacitor to a voltage that is proportional to a phase difference between a test clock signal from the PLL and a reference clock signal that can be assumed to be ideal. Additionally, the analog jitter measurements are digitized and processed (for instance, using digital signal processing) to generate an estimate of jitter.