PLL Lock Detection Using Hysteresis Thresholds Under PVT Noise
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Phase locked loop (PLL) circuits face instability due to variations in process, voltage, and temperature (PVT) factors, leading to incorrect lock state detection and potential malfunctions, as existing lock detection circuits are prone to mistaking noise-induced jitter for lock or unlock states.
Innovation Solution
A lock detector is designed with a clock generating circuit, phase-frequency detector, charge pump, voltage-controlled oscillator, and logic gates to determine lock and unlock states using hysteresis-based reference values, generating a lock detection signal that differentiates between stable lock and unlock states by controlling pulse widths and removing noise components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single reference value is used for lock detection, then the detection threshold is simple to set, but the system becomes unstable under PVT variations and noise
Solution Approach 1:
The single reference value is segmented into two distinct reference values: a first reference value for determining lock state and a second reference value for determining unlock state. This segmentation allows each reference value to be optimized for its specific function, improving reliability without significantly increasing complexity.
Solution Approach 2:
The reference value parameter is changed from a single fixed value to multiple variable values (first and second reference values) that can be adjusted based on operating conditions. This parameter change enables the system to adapt to PVT variations and noise, resolving the stability issue.
2Measurement precision
If the reference value is set low to detect lock accurately, then lock detection precision is improved, but noise-induced jitter causes false unlock detection
Solution Approach 1:
The detection thresholds are segmented into two levels: a lower first reference value for accurate lock detection and a higher second reference value for preventing false unlock detection. This segmentation resolves the contradiction by allowing precise lock detection while filtering out noise-induced false positives.
Solution Approach 2:
The system uses feedback from the phase difference comparison to control pulse width, which is then used to generate the lock detection signal. This feedback mechanism ensures that only sustained phase differences exceeding the second reference value trigger unlock detection, preventing false positives from transient noise.
3Reliability
If the reference value is set high to avoid false lock detection, then false lock detection is reduced, but the system cannot accurately detect true lock state
Solution Approach 1:
The reference values are segmented into two distinct levels: the first reference value remains low to ensure accurate lock detection, while the second reference value is set high to prevent false lock detection. This dual-level segmentation allows the system to maintain both sensitivity and specificity in lock state detection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution stabilizes PLL circuit operations by precisely determining lock and unlock states, reducing the likelihood of malfunctions and maintaining system stability despite noise and external factor variations.
Implementation Method 1
a phase-frequency detector configured to generate an up signal and a down signal according to a phase difference between a division clock signal obtained by dividing the output clock signal and the reference clock signal
Implementation Method 2
control a pulse width of the up signal when the phase of the division clock signal trails that of the reference clock signal, and control a pulse width of the down signal when the phase of the division clock signal leads that of the reference clock signal, a charge pump configured to pump a voltage according to the pulse widths of the up signal and the down signal and generate a control voltage
Implementation Method 3
a voltage-controlled oscillator (VCO) configured to vary the frequency of the output clock signal in response to the control voltage
Implementation Method 4
A lock detector is designed with a clock generating circuit, phase-frequency detector, charge pump, voltage-controlled oscillator, and logic gates to determine lock and unlock states using hysteresis-based reference values
Data Source
AI summary
Provided are a phase locked loop (PLL) circuit, a lock detector employable with a PLL circuit, a system including such a PLL circuit and/or lock detector, and a method of detecting a lock/unlock state of a PLL circuit. The PLL circuit may include a clock generating circuit configured to generate an output clock signal having a predetermined frequency in synchronization with a reference clock signal. The lock detector may be configured to determine that the PLL circuit is in a lock state when a phase difference between the reference clock signal and the output clock signal is equal to or less than a first reference value, determine that the PLL circuit is in an unlock state when the phase difference between the reference clock signal and the output clock signal is greater than a second reference value, and generate a lock detection signal.