PLL Loop Band Switching for Fast Chirp Settling and Low Phase Noise
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Solution Overview
Problem
Existing PLL circuits in FMCW radars face challenges in achieving high-speed and high-accuracy frequency modulation due to trade-offs between chirp speed, linearity error, and frequency deviation, leading to increased noise and inaccurate measurements.
Innovation Solution
A PLL circuit with dynamic loop band switching, where the loop band is narrowed during chirp operations for improved phase noise characteristics and widened during non-chirp periods to reduce settling time and enhance frequency accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the loop band is widened to reduce settling time, then frequency switching speed is improved, but phase noise characteristics deteriorate
Solution Approach 1:
The patent implements dynamic loop band switching by detecting chirp operation states and automatically adjusting the loop band width accordingly. During chirp operations, the loop band is narrowed to suppress phase noise, while during non-chirp periods, the loop band is widened to reduce settling time. This dynamic adaptation resolves the contradiction between speed and noise by making the loop band a variable parameter rather than a fixed design constraint.
Solution Approach 2:
The invention changes the loop band parameter based on operational phase. A loop band switching control unit monitors the chirp operation state and adjusts the loop band width parameter dynamically. This parameter change strategy allows the system to optimize performance for different operational requirements, achieving both fast switching and low noise when needed.
2Object-affected harmful factors
If the loop band is narrowed to improve phase noise characteristics, then noise is reduced, but settling time increases
Solution Approach 1:
The system dynamically adjusts the loop band width based on the chirp operation state detected by the chirp operation state detection unit. During non-chirp periods, the loop band is widened to minimize settling time, while during chirp operations, it is narrowed to reduce phase noise. This dynamic behavior eliminates the need to compromise between noise and settling time.
Solution Approach 2:
The loop band switching operates periodically in sync with the chirp operation cycles. The system alternates between wide loop band mode (for fast settling during non-chirp periods) and narrow loop band mode (for low noise during chirp operations). This periodic adjustment aligns the loop band configuration with the operational requirements of each phase.
3Productivity
If high-speed FMCW modulation is implemented, then productivity is improved, but frequency error increases due to linearity errors
Solution Approach 1:
The system performs preliminary detection of the chirp operation state before executing frequency modulation. The chirp operation state detection unit identifies upcoming chirp operations, allowing the loop band switching control unit to pre-adjust the loop band width to appropriate settings. This preliminary action ensures the PLL is optimally configured before high-speed modulation begins, minimizing frequency errors.
Solution Approach 2:
The invention implements a feedback mechanism where the chirp operation state detection unit continuously monitors the operational phase and feeds this information to the loop band switching control unit. This feedback loop enables real-time adaptation of the loop band width, ensuring the PLL maintains frequency accuracy even during high-speed FMCW modulation by adjusting parameters based on actual operational conditions.
Data Source
AI summary
A PLL circuit including a digitally controlled oscillator outputting, as an output signal, a signal having a frequency modulated according to a control signal, a detection unit detecting a difference in at least one of a ratio or a phase of a frequency between the output signal and a reference signal, a digital loop filter smoothing an output indicating the difference output from the detection unit and outputs, as the control signal, a resulting output to the digitally controlled oscillator, a control signal storage unit storing, as a previous control signal, a digital value based on the control signal output from the digital loop filter in a predetermined period immediately before end of a chirp operation period, and a control unit controlling the digital loop filter such that the control signal output from the digital loop filter immediately after start of the chirp operation period is the previous control signal.