PLL-OCC Clock Path Balancing for Stuck-at Test Timing
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Solution Overview
Problem
Existing design-for-test (DFT) IC chips face timing imbalances during stuck-at capture and at-speed capture phases, leading to inaccuracies in fault detection.
Innovation Solution
A test circuit in an integrated circuit (IC) is designed with a phase-locked loop (PLL) circuit that outputs balanced clock signals for both capture and shift phases, ensuring equal clock paths through an on-chip clock controller (OCC) and clock trees.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different clock paths are used for at-speed capture and stuck-at capture, then each testing phase can use optimized clock signals, but timing imbalances occur during stuck-at capture
Solution Approach 1:
The clock path is segmented into multiple selectable routes. During at-speed capture, one path configuration is used; during stuck-at capture, a different path configuration is used. The segmentation allows each phase to have optimized clock delivery while maintaining timing balance within each phase through dedicated path optimization.
Solution Approach 2:
The clock distribution system dynamically reconfigures the clock paths based on the testing phase. The system transitions between different clock delivery configurations - using one path configuration for at-speed capture and another for stuck-at capture, ensuring optimal timing balance for each specific testing scenario.
2Manufacturing precision
If a single clock path is used for both capture phases, then timing balance can be maintained, but the system cannot optimize clock signals for specific testing requirements
Solution Approach 1:
The clock distribution system is designed with multi-functionality to serve both at-speed capture and stuck-at capture requirements. By incorporating selectable clock paths and configuration options, the system achieves universal applicability across different testing phases while maintaining timing balance through phase-specific path optimization.
Solution Approach 2:
The system changes operational parameters (clock path selection, signal routing configuration) based on the testing phase requirements. During at-speed capture, parameters are set for high-speed operation; during stuck-at capture, parameters are adjusted for timing-critical operations, allowing optimization for each phase while maintaining overall system versatility.
Data Source
AI summary
A test-circuit includes a PLL-divider outputting first and third clock-signals as PLL clock-signals during functional mode and a capture-phase of transition and stuck-at-modes, and outputting a second clock-signal based upon an external clock-signal as an ATE clock-signal during a shift-phase of the transition and stuck-at-mode. An OCC passes the clock-signals in functional mode, transition capture mode, and stuck-at capture mode through sub-paths within first paths within first and second clock selection circuits so the first and third clock-signals are passed through less than the entire first paths, the sub-paths being first and second functional clock paths. In shift phase of transition and stuck-at-modes, the OCC passes the second clock-signal through sub-paths within second paths within the first and second clock selection circuits during the shift-phase so the second clock-signal is passed through less than the entire second paths, and through the first and second functional clock paths during the shift-phase.