Phase-Locked Loop Offset Current Presetting for Fast Lock
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Solution Overview
Problem
Existing phase locked loops (PLLs) experience long lock times, especially as the operating frequency range widens, leading to increased preparation time for synchronizing output signals with input data signals.
Innovation Solution
A phase locked loop design that includes a main voltage-controlled oscillator with offset current adjustment, a phase frequency detector, and an offset current setter. The offset current setter uses n sample voltage-controlled oscillators and counters to generate an offset current setting code, ensuring the main voltage-controlled oscillator's offset current is similar to that of a reference sample oscillator, thereby reducing lock time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the operating frequency range of the phase locked loop is widened, then the adaptability of the device is improved, but the lock time becomes longer
Solution Approach 1:
The patent applies preliminary action by using sample voltage-controlled oscillators to pre-determine the appropriate offset current setting code before the main voltage-controlled oscillator begins operation. The offset current setter compares frequencies using counters and selects the optimal offset current in advance, so when the main VCO starts, it is already configured with the correct offset current for the input signal frequency range. This preliminary configuration significantly reduces the lock time while maintaining wide frequency range adaptability.
2Adaptability or versatility
If the voltage-controlled oscillator operates over a wider frequency range, then the adaptability is improved, but the time for control voltage to reach target value increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the offset current parameter based on the input signal frequency. The offset current setter measures the input signal frequency and selects different offset current setting codes from a predefined set, effectively changing the offset current parameter to match the operating frequency range. This allows the VCO to operate efficiently across a wide frequency range while reducing the control voltage settling time, as the offset current is optimized for each frequency band.
3Productivity
If the lock time is reduced, then the operational speed is improved, but the complexity of the frequency setting mechanism increases
Solution Approach 1:
The patent applies segmentation by dividing the frequency setting function into separate components: multiple sample voltage-controlled oscillators, frequency comparison counters, and an offset current setter. Each component performs a specific sub-function (frequency generation, frequency comparison, code selection), which simplifies the overall design while achieving fast lock time. The segmentation allows parallel operation of multiple sample VCOs to quickly determine the optimal offset current without requiring a complex monolithic frequency synthesis mechanism.
Data Source
AI summary
A phase locked loop includes a main voltage-controlled oscillator for which an oscillation frequency is adjusted by an offset current and a control voltage (Vctrl), the offset current being set by an offset current setting code (VCO_CON), a phase frequency detector configured to adjust the control voltage by comparing an output signal (mCLK) of the main voltage-controlled oscillator and an input data signal (Data), and an offset current setter configured to generate the offset current setting code for setting the offset current of the main voltage-controlled oscillator. The offset current setter includes n sample voltage-controlled oscillators configured to generate n signals with different frequencies, respectively, and n counters configured to compare frequencies of each of the signals (sCLK) output from the n sample voltage-controlled oscillators and the input data signal, and is configured to generate the offset current setting code based on a comparison result of the n counters.