PLL Loop Division Control for Jittery Packet Arrival Timing
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Solution Overview
Problem
Existing phase locked loops (PLLs) struggle to maintain correspondence between input and output data due to jitter in packet arrival times, potentially causing buffer overflow in automotive Ethernet systems.
Innovation Solution
A circuit and method to adjust the loop division factor (LDF) of a PLL based on a moving average of jitter, updating the LDF more frequently for static jitter and less frequently for variable jitter to compensate for timing deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the local clock frequency is kept steady to ensure accurate serialization, then the serialization accuracy is improved, but the correspondence between input packets and output bits deteriorates due to jitter in packet arrival times
Solution Approach 1:
The loop division factor (LDF) of the PLL is made dynamically adjustable based on detected jitter conditions. The system transitions from a static LDF to a dynamic LDF that adapts to varying packet arrival patterns, allowing the clock frequency to be modulated in response to jitter while maintaining overall stability for accurate serialization.
Solution Approach 2:
The system changes the LDF parameter of the PLL based on measured jitter characteristics. By detecting packet arrival deviations and adjusting the LDF accordingly, the system modifies the clock frequency parameter to compensate for jitter, thereby maintaining both serialization accuracy and input-output correspondence.
2Reliability
If the LDF is adjusted frequently to track variable jitter, then the compensation accuracy is improved, but the system complexity and processing overhead increase
Solution Approach 1:
The system applies partial adjustment by updating the LDF only when necessary based on jitter detection thresholds. Rather than continuously adjusting the LDF at every packet arrival, the system performs adjustments selectively, reducing processing overhead while maintaining adequate compensation accuracy for variable jitter conditions.
Solution Approach 2:
The PLL system automatically detects jitter and self-adjusts its LDF without requiring external intervention. The system monitors its own input packet arrivals, calculates jitter, and modifies its own operating parameters, eliminating the need for complex external control mechanisms while maintaining compensation accuracy.
3Reliability
If the LDF is adjusted to compensate for jitter, then the correspondence between input and output data is improved, but the clock frequency stability deteriorates
Solution Approach 1:
The LDF adjustment is performed periodically based on detected jitter patterns rather than continuously. The system measures jitter over a period, determines the necessary compensation, and applies LDF adjustments at regular intervals, which maintains input-output correspondence while preventing excessive frequency variations that would destabilize the clock.
Solution Approach 2:
The system implements feedback control by monitoring packet arrival times, calculating jitter, and using this information to adjust the LDF. The adjusted LDF is then monitored to ensure it maintains frequency stability, creating a closed-loop system that balances compensation accuracy with clock stability through continuous feedback.
Data Source
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AI summary
In accordance with various embodiments of the present disclosure, a circuit to adjust a loop division factor (LDF) of a phase locked loop (PLL) is provided. In some embodiments, the circuit comprises processing circuitry configured to (1) determine an amount of jitter of a received input frequency comprising a plurality of input ticks, the amount of jitter being an amount of variation between an expected receipt of each of the plurality of input ticks and an actual receipt thereof, (2) determine a moving average of the determined amount of jitter, (3) determine an adjusted LDF based on the determined moving average of the determined amount of jitter, and (4) output the adjusted LDF to a PLL.