Fractional-N PLL Phase Compensation for Low-Range TDCs
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Solution Overview
Problem
Current phase-locked loops (PLLs), particularly fractional-n PLLs in telecommunication systems, face challenges in reducing the dynamic range requirements of time-to-digital converters (TDCs) while maintaining performance, leading to high current consumption and complexity due to phase noise and spurious content issues.
Innovation Solution
A phase compensator module is introduced to configure the PLL, reducing the dynamic range of the TDC by modifying the output of the sigma-delta module and providing a feedforward signal to boost the TDC output, allowing the PLL to operate with a low dynamic range while maintaining noise performance comparable to high-order sigma delta operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-order sigma delta modulation is used for fractional noise suppression, then noise performance is improved, but TDC dynamic range requirements increase leading to higher current consumption and complexity
Solution Approach 1:
The patent segments the TDC operation into two distinct parts: a coarse counter that handles large phase deviations and a fine TDC that handles small phase adjustments. This segmentation allows the fine TDC to operate with reduced dynamic range while the coarse counter absorbs the bulk of the dynamic range requirements, thereby maintaining noise performance without excessive TDC complexity
Solution Approach 2:
The patent introduces a phase offset compensator as an intermediary component between the PFD and TDC. This compensator dynamically adjusts the phase offset based on the sigma-delta modulator output, effectively preprocessing the signal to reduce the dynamic range burden on the TDC while preserving the benefits of high-order sigma-delta modulation for noise suppression
2Use of energy by moving object
If TDC dynamic range is reduced to lower current consumption, then power efficiency is improved, but phase detection accuracy deteriorates
Solution Approach 1:
By dividing the phase detection function between a coarse counter and a fine TDC, the patent enables the fine TDC to operate with reduced dynamic range and lower current consumption while the coarse counter maintains overall phase detection accuracy by handling large phase deviations
Solution Approach 2:
The phase offset compensator performs preliminary action by pre-adjusting the phase offset based on the sigma-delta modulator output before the signal reaches the TDC. This preliminary compensation ensures that the TDC receives a pre-conditioned signal that requires less dynamic range while maintaining phase detection accuracy
Data Source
AI summary
A phase locked loop comprising a time to digital converter and a fractional-n feedback loop, the PLL being configurable by a phase compensator module to reduce the dynamic range of the TDC required to maintain PLL performance.