PLL Phase Divider Clock Circuit for Multi-Rate IC Timing
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Solution Overview
Problem
Integrated circuits (ICs) face challenges with multiple clock signals required for different circuit blocks, leading to noise, timing issues, increased size, power consumption, and cost due to the use of multiple phase locked loops (PLLs) and off-chip crystal oscillators.
Innovation Solution
A single clock circuit utilizing a phase locked loop (PLL) and multiple phase dividers generates multiple clock signals with varying rates by producing phase-offset output oscillations, which are then controlled to produce specific clock signals for different circuit blocks, reducing the need for separate PLLs and off-chip oscillators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple PLLs are used to generate different clock signals for different circuit blocks, then each circuit block can have its required clock signal, but noise and timing issues occur between circuit blocks
Solution Approach 1:
The patent merges multiple PLL functions into a single PLL by adding a phase divider circuit. The single PLL generates a master clock signal that is then divided into multiple different frequency clock signals for different circuit blocks, eliminating the need for multiple separate PLLs and reducing noise and timing issues.
Solution Approach 2:
The single PLL with phase divider serves multiple functions: it generates the master clock signal and simultaneously produces multiple different frequency clock signals for various circuit blocks through the phase divider, making one component perform the work of multiple components.
2Adaptability or versatility
If multiple PLLs are used to generate different clock signals, then each circuit block receives its required clock signal, but the die area increases
Solution Approach 1:
The patent combines multiple PLL circuits into a single PLL with an integrated phase divider, significantly reducing the die area occupied by clock generation circuitry while maintaining the capability to provide multiple different frequency clock signals to different circuit blocks.
3Adaptability or versatility
If multiple PLLs are used to generate different clock signals, then each circuit block receives its required clock signal, but power consumption increases
Solution Approach 1:
The patent merges multiple power-consuming PLL circuits into a single PLL with a phase divider, reducing overall power consumption while still providing multiple different frequency clock signals to various circuit blocks through the phase division mechanism.
4Measurement precision
If off-chip crystal oscillators are used for multiple PLLs, then accurate clock signals are generated, but device cost increases
Solution Approach 1:
The patent consolidates the need for multiple off-chip crystal oscillators into a single on-chip PLL with phase divider, reducing component count and assembly costs while maintaining clock signal accuracy through the phase division mechanism.
Data Source
AI summary
A clock system includes a phase locked loop, a phase divider, and a control module. The phase locked loop (PLL) produces a plurality of phase-offset output oscillations. The phase divider generates a clock signal from one or more of the plurality of phase-offset output oscillations based on a phase divider control signal. The control module generates the phase divider control signal based on a desired setting for the clock signal.