PLL Frequency Generator With Calibrated Phase Error Compensation
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Solution Overview
Problem
Existing PLL frequency generators face challenges in achieving high signal/noise ratios at higher frequency resolutions and target frequency values, especially due to phase jitter and additional phase errors caused by fractional-N division, leading to increased realization costs and energy consumption.
Innovation Solution
A PLL frequency generator design that includes a voltage-controlled oscillator, a switchable frequency divider, a switchable delay unit, a phase detector, and a calibration unit, where the calibration unit derives control signals from the reference signal to compensate for phase errors, allowing for instantaneous compensation of phase errors and reducing energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If fractional-N division is used to achieve high frequency resolution, then frequency resolution is improved, but signal/noise ratio deteriorates due to additional phase errors
Solution Approach 1:
The patent applies preliminary action by compensating for the phase error in advance before it affects the output signal. The phase error compensation unit calculates and applies the necessary phase correction based on the fractional part of the division ratio, thereby preventing the degradation of signal/noise ratio before it occurs.
Solution Approach 2:
The patent introduces a phase error compensation unit as an intermediary component between the frequency divider and the output. This intermediary unit specifically addresses the phase errors introduced by fractional-N division, allowing the system to maintain both high frequency resolution and good signal/noise ratio.
2Reliability
If phase compensation circuit with delay lines is used to compensate phase errors, then signal/noise ratio is improved, but device complexity and energy consumption increase drastically
Solution Approach 1:
The patent extracts only the essential function needed for phase error compensation - specifically the phase correction based on the fractional division part - rather than using complex delay lines and tuning circuits. This extracted approach maintains signal/noise ratio while significantly reducing device complexity and energy consumption.
Solution Approach 2:
The patent replaces the mechanical/physical delay line system with a digital/algorithmic phase error compensation mechanism. Instead of physically delaying signals through multiple delay elements, the system calculates and applies phase corrections digitally, thereby reducing hardware complexity while maintaining compensation effectiveness.
3Measurement precision
If tuning circuit operates continuously to adjust delay elements, then phase compensation accuracy is improved, but energy consumption increases
Solution Approach 1:
The patent implements periodic action by updating the phase compensation only when the division ratio changes or at specific intervals, rather than continuously adjusting. This approach maintains phase compensation accuracy while dramatically reducing the energy consumption of the tuning circuit, as it operates only when necessary.
Data Source
AI summary
A PLL frequency generator is disclosed for generating an output signal with a settable target frequency, comprising a) a voltage-controlled oscillator for generating the output signal depending on a control voltage, b) a switchable frequency divider, which is connected to the voltage-controlled oscillator and is designed to derive a frequency-divided signal whose instantaneous frequency depends on a value of an adjustable divisor, from the output signal c) a switchable delay unit, which is connected to the frequency divider and is designed to generate a delayed signal in that the frequency-divided signal is delayed by delay times that in each case depend on a control word and a control signal, and d) a phase detector, which is connected to the switchable delay unit and is designed to determine the phase difference between a reference signal and the delayed signal and to provide it for the generation of the control voltage. According to the invention, a calibration unit is provided, which is connected to the switchable delay unit and is designed to derive the control signal from the reference signal.