PLL Phase Error Threshold Detection for Jitter Control
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Solution Overview
Problem
Phase locked loop devices in electronic devices are adversely affected by power fluctuations and transient noise signals, leading to excessive phase error, jitter, and drift, which can cause undesirable behavior in synchronized modules.
Innovation Solution
A phase locked loop device with a phase detector, charge pump, voltage-controlled oscillator, and divider that measures phase differences between a reference clock signal and an output clock signal, generating pulses indicative of phase errors, and a compare module that asserts trigger signals based on programmed thresholds to adjust the clock signal frequency and phase, while a storage module records phase error information for diagnostic analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase locked loop devices are used to generate clock signals, then clock signal generation is achieved, but power fluctuations and transient noise signals cause excessive phase error, jitter, and drift
Solution Approach 1:
The patent implements a feedback mechanism where the phase detector continuously monitors the phase difference between the reference clock signal and the output clock signal, and adjusts the output signal accordingly to maintain phase lock and reduce errors caused by power fluctuations and noise
Solution Approach 2:
The phase detector acts as an intermediary component that measures phase differences and generates control signals to compensate for disturbances, mediating between the reference signal and the output signal to maintain stability
2Measurement precision
If phase detector measures phase differences and generates pulses, then phase error detection is achieved, but device complexity increases
Solution Approach 1:
The patent replaces complex analog phase measurement mechanisms with a digital approach using a phase detector that outputs digital pulses representing phase differences, simplifying the overall system while maintaining measurement precision
3Reliability
If compare module asserts trigger signals based on thresholds, then clock signal regulation is improved, but device complexity increases
Solution Approach 1:
The compare module monitors phase error parameters and asserts trigger signals when thresholds are exceeded, dynamically adjusting operating parameters to maintain clock signal regulation while using programmable thresholds to adapt to different conditions
Data Source
AI summary
A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal provided to a device module. The phase detector provides a pulse having a width indicative of the phase difference. If the phase difference exceeds one of a plurality of threshold values, an indicator can be asserted. Based on the indicator, a control module can take remedial action, such as providing a different clock signal to the device module or triggering an interrupt at a processor device.