PLL Phase Error Sign Generation for Fractional Spur Reduction
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Solution Overview
Problem
Fractional-N phase-locked loops (PLLs) in wireless communication systems suffer from fractional spurs due to nonlinearity in digital-to-time converters (DTCs), which degrade integrated phase noise (IPN) characteristics.
Innovation Solution
A phase-locked loop (PLL) circuit with a reference voltage generation circuit that adjusts a fixed and variable gain value to scale phase error sign signals, using a delta-voltage DAC and delta-sigma modulator to generate an accurate reference voltage, thereby reducing fractional spurs and improving IPN.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a digital-to-time converter (DTC) is used in a fractional-N PLL, then frequency synthesis capability is improved, but nonlinearity of the DTC causes an increase in fractional spurs
Solution Approach 1:
The patent implements a feedback mechanism where the phase error sign signal is fed back to adjust the DTC control code. The sign generator detects the sign of the phase error signal and uses this information to iteratively adjust the DTC control code, creating a closed-loop system that compensates for DTC nonlinearity and reduces fractional spurs.
Solution Approach 2:
The system performs self-calibration by using its own phase error signal to automatically adjust the DTC control code. The sign generator and control logic enable the system to self-correct for nonlinearity without requiring external calibration equipment or manual adjustment.
2Measurement precision
If the phase error signal amplitude is increased to improve detection accuracy, then phase error detection precision is improved, but the risk of overflow in subsequent processing stages increases
Solution Approach 1:
The patent extracts only the sign information (positive or negative) from the phase error signal using a sign generator, rather than processing the full amplitude information. This separates the essential directional information from the potentially problematic amplitude variations, preventing overflow while maintaining detection accuracy.
Solution Approach 2:
The system transforms the phase error signal from its original voltage domain with varying amplitudes into a binary sign domain with only two possible values. This parameter transformation eliminates the overflow risk associated with large amplitude variations while preserving the phase error detection capability.
3Device complexity
If conventional PLL design is used, then circuit simplicity is maintained, but fractional spurs cannot be effectively reduced
Solution Approach 1:
The patent segments the phase detection function into two distinct components: a phase detector that generates the phase error signal and a separate sign generator that extracts the sign information. This segmentation allows each component to be optimized for its specific function, reducing fractional spurs while adding minimal overall complexity.
Solution Approach 2:
The sign generator acts as an intermediary component between the phase detector and the DTC control logic. It processes the phase error signal to extract essential information in a form that is optimal for controlling the DTC, thereby reducing fractional spurs without significantly increasing system complexity.
Data Source
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AI summary
A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator configured to generate an output clock signal of the PLL circuit, a phase detector configured to generate a phase error signal representing a phase difference between a first clock signal based on a reference clock signal and a second clock signal based on the output clock signal, a comparator configured to generate a phase error sign signal based on a reference voltage and the phase error signal, and a reference voltage generation circuit configured to scale first and second sign values of the phase error sign signal based on a fixed gain value and a variable gain value, respectively, and generate the reference voltage based on the scaled first and second sign values.