PLL Phase Interpolator Segmentation for Lower-Power Fine Phase Tuning
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Solution Overview
Problem
Conventional phase interpolators in phase-locked loops (PLLs) consume substantial power and occupy large circuit areas, making them inefficient for fine-tuning phase differences in clock signals.
Innovation Solution
The implementation of a phase interpolator with segmented digital-to-analog converters (DACs) using thermometer and binary coding schemes, along with a time-to-digital converter for calibration, reduces power consumption and circuit area while maintaining high interpolation accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional phase interpolators are used to achieve fine phase tuning, then phase interpolation capability is provided, but power consumption and circuit area increase substantially
Solution Approach 1:
The phase interpolator is divided into multiple sub-interpolators, each handling a portion of the total phase range. This segmentation allows each sub-interpolator to use fewer delay elements while collectively providing fine phase resolution across the entire range, thereby reducing power consumption and area while maintaining interpolation accuracy.
Solution Approach 2:
The patent introduces a two-dimensional phase interpolation approach using in-phase (I) and quadrature (Q) components. By interpolating phase in both I and Q dimensions and combining the results, the system achieves fine phase resolution without requiring a single complex interpolator with many delay elements, thus reducing power and area.
2Measurement precision
If conventional phase interpolators are used to achieve fine phase tuning, then phase interpolation capability is provided, but circuit area increases substantially
Solution Approach 1:
The phase interpolator is divided into multiple sub-interpolators, each handling a portion of the total phase range. This segmentation allows each sub-interpolator to use fewer delay elements while collectively providing fine phase resolution across the entire range, thereby reducing power consumption and area while maintaining interpolation accuracy.
Solution Approach 2:
The patent combines the outputs of multiple sub-interpolators (or I and Q interpolators) to achieve the final phase-interpolated signal. This merging approach allows the system to achieve fine phase resolution through coordination of simpler units rather than requiring a single large complex interpolator, thus reducing total circuit area.
3Adaptability or versatility
If fractional divider with phase interpolator is used, then non-integer frequency division is achieved, but power consumption and area increase
Solution Approach 1:
The phase interpolator in the fractional divider is segmented into sub-interpolators, reducing the number of delay elements required while maintaining the ability to achieve any fractional division ratio. This segmentation lowers power consumption while preserving frequency division flexibility.
Solution Approach 2:
The use of I-Q dimensionality in the fractional divider allows flexible frequency division by controlling the phase relationship between I and Q components. This approach provides adaptability for various division ratios without requiring a large number of delay elements, thus reducing power consumption while maintaining versatility.
Data Source
AI summary
Phase-locked loop circuitry is provided that includes a time-to-digital converter, a first frequency divider circuit coupled to an output of the time-to-digital converter, and a second frequency divider circuit coupled between the first frequency divider circuit and an input of the time-to-digital converter and having a phase interpolator with a plurality of delay circuits forming a first digital-to-analog converter (DAC) circuit and a second digital-to-analog converter (DAC) circuit separate from the first DAC circuit. The phase interpolator can be calibrated using the time-to-digital converter.