Fractional PLL Quantization Extraction for Noise Shaping
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Solution Overview
Problem
Existing phase-locked loop (PLL) oscillators face challenges in effectively shaping quantization noise without increasing semiconductor die area or power consumption, and maintaining noise shaping when transmission path delays are mismatched.
Innovation Solution
A fractional PLL design that incorporates quantization extraction and masking logic to capture and preserve quantization information, using a nested frequency and quantization extraction loop to generate a clock signal with shaped quantization noise, while maintaining charge pump operation in the linear region and handling delay mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If quantization noise shaping is implemented in existing PLL oscillators, then noise shaping performance is improved, but semiconductor die area and power consumption increase
Solution Approach 1:
The patent extracts quantization information from the frequency divider output signal and processes it separately through quantization extraction circuitry. By taking out only the essential quantization noise components and processing them through a dedicated but compact extraction loop, the design achieves noise shaping without requiring extensive additional circuitry, thus improving noise shaping performance while minimizing die area increase
Solution Approach 2:
The quantization extraction loop is nested within the existing frequency extraction loop architecture. The quantization extraction circuitry is integrated into the PLL structure, with the extraction loop nested inside the main frequency synthesis path. This nesting allows shared resources and reduces overall circuit complexity, achieving noise shaping without proportional increases in die area
2Measurement precision
If quantization noise shaping is implemented in existing PLL oscillators, then noise shaping performance is improved, but power consumption increases
Solution Approach 1:
The patent extracts only the necessary quantization information from the frequency divider output rather than processing the entire signal path. By taking out and processing only the quantization components through the extraction loop, power consumption is minimized while achieving the desired noise shaping performance
Solution Approach 2:
The quantization extraction circuitry performs partial processing - it extracts and shapes only the quantization noise components rather than processing the entire signal spectrum. This partial action approach achieves noise shaping performance with reduced computational and power resources compared to full-signal processing approaches
3Device complexity
If conventional PLL design is used, then circuit simplicity is maintained, but noise shaping capability is lost when transmission path delays are mismatched
Solution Approach 1:
The patent introduces a quantization extraction loop with feedback path that specifically addresses transmission path delay mismatches. The feedback mechanism monitors and corrects for delay variations, maintaining noise shaping capability even when transmission path delays are mismatched, while adding minimal complexity to the conventional PLL structure
Solution Approach 2:
The quantization extraction circuitry acts as an intermediary between the frequency divider and the phase frequency detector. This intermediary component processes the quantization information and provides compensation for transmission path delay mismatches, enabling noise shaping to function correctly despite timing variations in the signal paths
Data Source
AI summary
An example apparatus includes quantization feedback circuitry (QFC) including an input terminal coupled to an output terminal of voltage-controlled oscillator (VCO) circuitry and an input terminal coupled to an output terminal of first frequency divider circuitry (FDC). The example apparatus also includes second FDC including an output terminal coupled to an input terminal of phase frequency detector (PFD) circuitry and an input terminal coupled to an output terminal of the first FDC. Also, the example apparatus includes masking logic circuitry including an output terminal coupled to an input terminal of the QFC, an input terminal coupled to the output terminal of the VCO circuitry, and an input terminal coupled to the output terminal of the second FDC. The example apparatus also includes adder circuitry including an input terminal coupled to an output terminal of the PFD circuitry and an input terminal coupled to an output terminal of the QFC.