PLL Re-Lock Control for Fast Phase Recovery Without Clock Glitches
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Solution Overview
Problem
Phase-locked loops (PLLs) often take a long time to regain phase-lock when they go out of phase-lock, especially due to changes in the input clock phase, which can be undesirable in certain environments.
Innovation Solution
A PLL implementation that includes a phase locking block with gating logic and a synchronizer to rapidly re-establish phase-lock within two cycles of the input clock, using a phase-to-digital converter, digital filter, and a digitally controlled oscillator, while preventing glitches in the feedback clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PLL operation is used, then the PLL can maintain stable operation, but it takes a long time to regain phase-lock when out of phase-lock
Solution Approach 1:
The patent applies preliminary action by detecting phase-lock loss in advance and proactively initiating a forced re-lock sequence. The phase locking block monitors the phase detector output and, upon detecting that the PLL is out of phase-lock, immediately forces the charge pump to operate in a re-lock mode, preparing and executing the correction before the phase error can significantly degrade system performance.
Solution Approach 2:
The patent employs feedback mechanisms where the phase detector continuously monitors the phase difference between input and feedback clocks and feeds this information back to the phase locking block. This feedback loop enables real-time detection of phase-lock status and triggers appropriate corrective actions, ensuring the PLL rapidly returns to locked state while maintaining stability through continuous monitoring and adjustment.
2Loss of time
If the PLL rapidly re-establishes phase-lock within two cycles, then the time to achieve phase-lock is minimized, but glitches may occur in the feedback clock
Solution Approach 1:
The patent introduces an intermediary mechanism in the form of a synchronizer or gating logic between the charge pump and the feedback clock path. This intermediary component buffers and conditions the rapid switching signals during forced re-lock, smoothing out transitions and preventing direct coupling of glitch-prone signals into the feedback clock, thus enabling fast re-lock without propagating harmful glitches.
Solution Approach 2:
The patent applies beforehand cushioning by implementing protection logic that anticipates potential glitches during forced re-lock operations. The gating mechanism is configured to suppress or filter out glitch-prone transitions in advance, cushioning the feedback clock path against harmful effects before they can propagate, thereby maintaining signal integrity during rapid phase-lock acquisition.
Data Source
AI summary
A phase-locked loop (PLL) provided according to an aspect of the present disclosure includes a phase detector, a low-pass filter, an oscillator, an output block and a phase locking block. The oscillator generates an intermediate clock and the output block generates each of successive cycles of a feedback clock on counting a pre-determined number of cycles of the intermediate clock. The phase locking block, upon detecting the PLL being out of phase-lock, controls the operation of the output block to obtain phase-lock in the PLL within two cycles of the input clock from the time of detection of the PLL being out of phase-lock.