Ring Oscillator Realignment Circuit for PVT-Resilient PLL Phase Noise
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Solution Overview
Problem
Current ring oscillators in phase-locked loop (PLL) circuits face challenges in reducing phase noise and frequency variations due to process, voltage, and temperature (PVT) variations, which affect their performance in ASICs.
Innovation Solution
The implementation of a ring oscillator with a controlling circuit and a delay chain that utilizes a realignment signal to adjust the phase of the waveform by enabling or disabling a pseudo pass-gate inverter, allowing for phase alignment without additional electronic components, thereby reducing power consumption and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ring oscillators are used in PLL circuits, then clock generation is achieved, but phase noise and frequency variations increase due to PVT variations
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing optimal delay values in lookup tables during the design phase. These lookup tables contain compensation values for various PVT conditions, allowing the ring oscillator to quickly retrieve and apply appropriate delay adjustments without real-time complex calculations, thereby maintaining stable frequency output under varying conditions
Solution Approach 2:
The patent changes the delay parameter of the ring oscillator by selecting different delay values from lookup tables based on detected PVT conditions. The controlling circuit adjusts the total delay through a selectable number of delay elements, dynamically changing the oscillator's frequency characteristics to compensate for PVT variations and maintain reliable phase noise performance
2Ease of operation
If additional electronic components are added for phase alignment, then phase adjustment capability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies self-service by enabling the ring oscillator to perform its own phase alignment through an internal controlling circuit. The controller detects phase errors and automatically adjusts delay elements within the oscillator structure itself, eliminating the need for external phase alignment components and reducing overall device complexity while maintaining full phase adjustment capability
Solution Approach 2:
The patent merges the phase alignment function with the ring oscillator structure by integrating delay elements and control logic directly into the oscillator circuit. This combination allows phase adjustment to be performed using the existing oscillator components rather than adding separate phase alignment hardware, thereby reducing device complexity and manufacturing cost
3Measurement precision
If fine frequency resolution is achieved in ring oscillator, then clock generation precision is improved, but sensitivity to PVT variations increases
Solution Approach 1:
The patent applies feedback by implementing a controlling circuit that continuously monitors the ring oscillator's output frequency and compares it against target values. Based on this feedback, the controller automatically adjusts delay elements to compensate for PVT-induced frequency drift, allowing the system to maintain fine frequency resolution while being insensitive to environmental variations
Solution Approach 2:
The patent uses preliminary action by pre-characterizing the ring oscillator's frequency response across various PVT conditions during manufacturing. Measured delay values are stored in lookup tables that enable the controlling circuit to select appropriate compensation values in advance, allowing the oscillator to maintain precise frequency resolution while compensating for PVT variations without real-time complex adjustments
Data Source
AI summary
A controlling circuit for ring oscillator is provided. First and second transistors of a first conductive type are coupled in series and between a node and a first power source. Third and fourth transistors of a second conductive type are coupled in parallel and between the node and a second power source. The node is coupled to an input of a delay chain of the ring oscillator. The second and third transistors are coupled in series and gates of the second and third transistors are configured to receive an output signal of the delay chain. When the first transistor is turned off and the fourth transistor is turned on, the node is pulled to a first logic level from a second logic level in order to align a phase of a waveform of the ring oscillator.