PLL Phase Signal Gating for EMI Noise Reduction

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Solution Overview

Problem

Conventional PLL circuits face challenges in reducing EMI noise due to peak power spectrum levels caused by system clock signals, requiring complex adjustments and mechanisms to optimize frequency dividing ratio switch-over timing, which can result in unstable bandwidth and ineffective noise reduction.

Innovation Solution

A PLL circuit design incorporating a resistor element between a potential and a signal line for the phase difference signal, enabling/disabling the phase difference signal to the low-pass filter, and using a counter to reset the phase difference signal, allowing the oscillation circuit to operate based on a predetermined potential, thereby spreading the power spectrum and reducing EMI noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-generated harmful factors

If conventional spread spectrum technology is used with frequency dividing ratio switch-over, then power spectrum spreading is achieved, but the mechanism becomes complex and bandwidth becomes unstable

Engineering Contradiction:
ImproveEMI noiseVSAvoidfrequency dividing ratio switch-over mechanism
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent extracts the spread spectrum function from the complex frequency dividing ratio switch-over mechanism. By using a dedicated spread spectrum control signal to directly control the phase difference signal enabling switch-over, the invention separates the spread spectrum control function from the frequency synthesis control, thereby simplifying the overall mechanism while maintaining power spectrum spreading capability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies preliminary action by pre-generating a spread spectrum control signal that determines the switch-over timing before the actual frequency synthesis operation. This predetermined control signal is used to enable/disable the phase difference signal in advance, ensuring stable and predictable bandwidth control without requiring complex real-time adjustments during operation.

Inventive Principle:
Principle #10Preliminary action

2Object-generated harmful factors

If frequency dividing ratio switch-over is adjusted to optimize spread spectrum, then EMI noise reduction is improved, but the adjustment process becomes complex and time-consuming

Engineering Contradiction:
ImproveEMI noise reductionVSAvoidoptimization adjustment time
Core Design Contradiction:
Object-generated harmful factorsVSLoss of time

Solution Approach 1:

The patent implements self-service by making the spread spectrum control signal self-determining. The control signal automatically generates the appropriate enabling/disabling timing for the phase difference signal based on predetermined spread spectrum parameters, eliminating the need for manual optimization adjustments. The system self-configures the frequency dividing ratio switch-over timing according to the spread spectrum requirements.

Inventive Principle:
Principle #25Self-service

3Reliability

If phase difference signal is continuously enabled for stable PLL operation, then lock stability is maintained, but peak power spectrum level increases causing more EMI noise

Engineering Contradiction:
ImprovePLL lock stabilityVSAvoidpeak power spectrum level
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies periodic action by using the spread spectrum control signal to periodically enable and disable the phase difference signal in a predetermined manner. This periodic switching creates the frequency dividing ratio change necessary for power spectrum spreading while maintaining sufficient phase lock stability during the enabled periods, thereby reducing peak power spectrum levels without completely sacrificing lock stability.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS8031015B2Phase-locked loop circuit
Publication Date: 2011.10.04 SEMICON COMPONENTS IND LLC
  • US8031015B2 patent drawing
  • US8031015B2 patent drawing
  • US8031015B2 patent drawing

AI summary

A PLL circuit is disclosed that comprises a controlling unit that switches at a predetermined timing to enable/disable the phase difference signal supplied from the phase comparator to the low pass filter; and a resistor element that is disposed between a predetermined potential and a signal line for supplying the phase difference signal from the phase comparator to the low pass filter, when the phase difference signal is enabled, the oscillation circuit performing oscillation operation based on the voltage signal corresponding to the phase difference signal, when the phase difference signal is disabled, the low pass filter being supplied with the predetermined potential through the resistor element to allow the oscillation circuit to perform oscillation operation based on the voltage signal generated depending on the supplied predetermined potential.