PLL Reconfiguration for Faster SSC-to-Non-SSC Clock Settling
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Solution Overview
Problem
Phase locked loops (PLLs) in data communication systems experience prolonged settling times when transitioning from spread spectrum clock (SSC) to non-SSC mode, leading to increased electromagnetic interference (EMI) and regulatory compliance issues.
Innovation Solution
A control circuit in the PLL is configured to effectuate a first configuration change upon deassertion of the SSC enable signal, reducing the time interval for the clock signal to settle to a constant frequency by adjusting loop parameters such as bandwidth and gain, thereby minimizing EMI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the PLL operates in SSC mode to reduce EMI, then electromagnetic interference is reduced, but the settling time when transitioning to non-SSC mode is prolonged
Solution Approach 1:
The patent applies dynamics by making the PLL configuration adjustable based on operating mode. The system dynamically switches between SSC and non-SSC configurations, allowing the loop bandwidth and other parameters to be optimized for each mode. This enables fast settling when transitioning from SSC to non-SSC mode while maintaining EMI reduction benefits when in SSC mode.
Solution Approach 2:
The patent changes physical parameters of the PLL based on the operating mode. Specifically, the loop bandwidth and other configuration parameters are modified when transitioning between SSC and non-SSC modes. This parameter adjustment allows the system to achieve fast settling time in non-SSC mode while maintaining effective EMI reduction in SSC mode.
2Object-affected harmful factors
If the PLL uses a fixed configuration for SSC mode, then EMI is reduced, but the transition to non-SSC mode experiences prolonged settling time and increased EMI
Solution Approach 1:
The system transitions from a fixed SSC configuration to a dynamic configuration that adapts based on the operating mode. The control circuit automatically adjusts PLL parameters when exiting SSC mode, ensuring reliable compliance with EMI regulations during transitions while maintaining the EMI reduction benefits during SSC operation.
Solution Approach 2:
The patent applies preliminary action by pre-configuring the PLL for fast settling before the transition to non-SSC mode is complete. The control circuit initiates configuration changes in advance, adjusting loop parameters proactively to ensure the PLL settles quickly and complies with EMI regulations, rather than reacting after the transition has already caused compliance issues.
3Loss of time
If the PLL transitions quickly from SSC to non-SSC mode, then settling time is reduced, but EMI regulations may not be met during transition
Solution Approach 1:
The control circuit performs preliminary configuration changes before the PLL fully transitions to non-SSC mode. By adjusting loop bandwidth and other parameters in advance, the system prepares for fast settling while maintaining EMI control during the transition period, thus meeting both settling time requirements and EMI regulations.
Solution Approach 2:
The system uses feedback mechanisms to monitor the PLL state during mode transitions and adjust configuration parameters accordingly. This feedback control ensures that the transition achieves fast settling time while maintaining EMI levels within regulatory limits, balancing speed and compliance requirements.
Data Source
AI summary
An apparatus, including: a phase locked loop (PLL) configured to generate a spread spectrum clock (SSC) clock signal where the SSC clock signal swings between a first frequency and a third frequency based on an SSC enable signal being asserted, or a non-SSC clock signal where the non-SSC clock signal is substantially constant at a second frequency based on the SSC enable signal being deasserted; and a control circuit configured to effectuate a first configuration change of the PLL in response to the SSC enable signal becoming deasserted, the first configuration change reducing a time interval between the SSC enable signal becoming deasserted and the non-SSC clock signal settling to substantially the second frequency.