PLL Startup Voltage Control for Fast Re-Locking at Low Power
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Solution Overview
Problem
Phase-locked loops (PLLs) in wireless communication systems and optical devices face challenges in reducing power consumption, particularly in maintaining phase and frequency stability while minimizing energy usage.
Innovation Solution
The implementation of a phase-locked loop circuit comprising a processing unit, a voltage-controlled oscillator, and a control unit that deactivates and activates the oscillator during power-down and power-on modes, respectively, using a start voltage stored in a capacitor to quickly stabilize the feedback clock, and utilizing a ring oscillator to reduce power consumption when not using a crystal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the voltage-controlled oscillator is continuously operated to maintain phase and frequency stability, then the clock generation accuracy is improved, but the power consumption increases
Solution Approach 1:
The patent applies preliminary action by storing a start voltage in a capacitor before the PLL enters power-down mode. This pre-stored voltage enables the VCO to quickly resume operation and lock onto the correct frequency when power is restored, eliminating the need for continuous operation while maintaining stability. The capacitor is charged during normal operation and discharges to provide the initial voltage spike needed for rapid re-locking.
Solution Approach 2:
The patent implements periodic action by alternating between active and power-down states based on operational needs. The PLL operates continuously only when clock generation is required, and enters power-down mode during idle periods. The control unit monitors the operational state and periodically switches between these modes, with the stored start voltage enabling rapid transitions back to the active state when needed.
2Use of energy by moving object
If the voltage-controlled oscillator is deactivated to reduce power consumption during power-down mode, then the energy usage is reduced, but the time to re-establish phase lock increases
Solution Approach 1:
The start voltage is stored in the capacitor during normal operation before power-down occurs. This preliminary storage of energy in the capacitor ensures that when the VCO needs to restart, the voltage is already available, eliminating delay. The capacitor acts as a pre-charged energy reservoir that can immediately discharge to kickstart the VCO oscillation.
Solution Approach 2:
The patent applies the skipping principle by using the stored start voltage to rapidly jump through the initialization phase of VCO operation. Instead of slowly ramping up the voltage or waiting for gradual stabilization, the pre-stored voltage provides an immediate voltage spike that forces the VCO to start oscillating quickly, rushing through the warm-up period and achieving phase lock much faster than conventional startup methods.
3Reliability
If a crystal oscillator is used to generate the reference clock for accurate frequency control, then the frequency stability is improved, but the power consumption increases compared to alternative oscillators
Solution Approach 1:
The reference clock is generated and stored in advance before the PLL needs to operate. During power-down mode, the crystal oscillator can be deactivated since the reference clock characteristics are already established. When power is restored, the system can quickly reinitialize using the pre-established reference parameters, eliminating the need for continuous crystal operation while maintaining frequency accuracy.
Solution Approach 2:
The patent applies copying by using the stored start voltage as a replica of the control voltage that was present during normal operation. Instead of requiring the crystal oscillator to continuously generate the reference signal, the system captures and stores the essential voltage characteristics and uses this copied information to rapidly restore the VCO to its correct operating state, reducing the need for continuous high-power reference generation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption by allowing the PLL to quickly enter a locked state during power-on mode and minimizing energy usage during idle periods, while maintaining accurate clock generation and frequency stability.
Implementation Method 1
a voltage-controlled oscillator, and a control unit. The processing unit generates a control voltage to a node according to a phase difference between a reference clock and a first feedback clock. The voltage-controlled oscillator generates the first feedback clock according to a voltage of the node.
Implementation Method 2
The voltage-controlled oscillator is deactivated and a start voltage is provided to the node in a power-down mode. The voltage-controlled oscillator is activated such that the voltage-controlled oscillator generates the first feedback clock according to the voltage of the node in a power-on mode. The voltage of the node is equal to the start voltage.
Data Source
AI summary
A phase-locked loop includes a processing unit, a voltage-controlled oscillator, and a control unit. The processing unit generates a control voltage to a node according to a phase difference between a reference clock and a first feedback clock. The voltage-controlled oscillator generates the first feedback clock according to a voltage of the node. The control unit deactivates the voltage-controlled oscillator and provides a start voltage to the node in a power-down mode, and activates the voltage-controlled oscillator to generate the first feedback clock according to the voltage of the node in a power-on mode. The control unit stops providing the start voltage in the power-on mode.