PLL Sub-Band Calibration for Faster Phase Lock
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Solution Overview
Problem
Conventional phase-locked loop (PLL) circuits require a long duration and high power consumption to achieve phase lock due to the need for successive comparison of numerous sub-bands to determine an optimal sub-band, which increases the time and energy required for phase lock.
Innovation Solution
A method and circuit that acquire multiple values of voltage-controlled oscillator capacitor array control signals and charge pump current signals in a calibration mode, allowing for direct determination of target values in the phase-locked mode to control the PLL, thereby reducing the duration and power consumption of achieving phase lock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the number of sub-bands of the VCO is increased to reduce gain KVCO and suppress phase noise, then phase noise is suppressed, but the number of comparisons required increases, resulting in longer duration and higher power consumption to achieve phase lock
Solution Approach 1:
The patent performs preliminary calibration before normal operation to establish a mapping relationship between frequency control words and optimal sub-bands. During calibration mode, the system pre-determines which sub-band corresponds to each frequency control word range, storing this information for rapid retrieval during phase-locked mode. This preliminary action eliminates the need for exhaustive comparisons during actual phase locking, thus reducing lock time while maintaining the benefit of multiple sub-bands for phase noise suppression
Solution Approach 2:
The patent segments the frequency control word range into multiple intervals, each associated with a specific sub-band. Instead of comparing all sub-bands equally during operation, the system divides the frequency spectrum into manageable segments and directly selects the appropriate sub-band based on the frequency control word interval, significantly reducing the number of comparisons needed while maintaining comprehensive coverage for phase noise suppression
2Object-affected harmful factors
If the number of sub-bands of the VCO is increased to reduce gain KVCO and suppress phase noise, then phase noise is suppressed, but the number of comparisons required increases, resulting in higher power consumption to achieve phase lock
Solution Approach 1:
The system performs the energy-intensive sub-band comparison process only once during calibration mode, storing the results for reuse. During normal phase-locked operation, the system simply retrieves the pre-determined optimal sub-band information without performing exhaustive comparisons, dramatically reducing power consumption while maintaining the ability to suppress phase noise through multiple sub-bands
Solution Approach 2:
The patent creates a lookup table or mapping structure during calibration that copies the relationship between frequency control words and optimal sub-bands. This copied information is then used during operation instead of重新 performing comparisons, reducing the computational energy required during phase locking while preserving the phase noise suppression benefits of multiple sub-bands
3Measurement precision
If conventional successive comparison method is used to determine optimal sub-band, then all sub-bands are evaluated, but the number of comparisons is large, resulting in longer duration to achieve phase lock
Solution Approach 1:
The system performs comprehensive sub-band evaluation during calibration mode and stores the optimal selections. During actual operation, it directly applies these pre-evaluated results based on the frequency control word, achieving both high selection accuracy and fast locking without the need for repeated exhaustive comparisons
Solution Approach 2:
The patent segments the frequency control word space into distinct intervals, each mapped to a specific optimal sub-band. This segmentation allows the system to determine the optimal sub-band through simple interval matching rather than exhaustive comparison, maintaining measurement precision while dramatically reducing the time required to achieve phase lock
Data Source
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AI summary
A phase-locked loop circuit and a method for controlling the phase-locked loop circuit are provided. Multiple values of a voltage-controlled oscillator capacitor array control signal respectively corresponding to multiple desired values of a frequency control word signal and multiple values of a charge pump current control signal respectively corresponding to the multiple desired values of the frequency control word signal are acquired in a calibration mode. In a phase-locked mode, a target value of the voltage-controlled oscillator capacitor array control signal corresponding to a target value of the frequency control word signal and a target value of the charge pump current control signal corresponding to the target value of the voltage-controlled oscillator capacitor array control signal are determined based on the data acquired in the calibration mode, to control the phase-locked loop circuit to achieve the phase lock. Therefore, an optimal sub-band is directly determined based on the acquired data, thereby shortening the duration spent by the phase-locked loop circuit on achieving phase lock and reducing power consumption of the phase-locked loop circuit in the process of achieving phase lock.