PLL Circuit Switching for Smooth External Clock Lock
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Solution Overview
Problem
Phase-locked loop (PLL) circuits experience frequency discontinuities and prolonged lock-up times when switching from an internal clock to an external clock, leading to issues such as voltage distortion and instability in applications like DC-DC converters.
Innovation Solution
The PLL is operated in a closed-loop configuration by aligning the PLL control node to the potential set by the external clock frequency, using an analog multiplexer and modified charge pump switches to maintain a smooth frequency transition, avoiding frequency jumps and reducing lock-up time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the PLL is enabled after the main system clock is already enabled, then the PLL can be activated to pace the internal clock, but a frequency jump occurs from the current clock frequency to the minimum PLL frequency
Solution Approach 1:
The patent applies preliminary action by pre-configuring the PLL control node potential to match the external clock frequency before PLL operation is enabled. This is achieved through modified charge pump switches and analog multiplexer that set the control node to the correct potential in advance, ensuring that when the PLL starts operating, there is no frequency jump and the transition from internal to external clock pacing is smooth and continuous.
2Ease of operation
If an analog multiplexer is used to switch PLL operation from open-loop to closed-loop oscillation, then the PLL can start operating at a fixed frequency, but an undesirable frequency jump occurs from the internal programmed clock frequency to the lowest frequency desired for starting PLL operation
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the potential at the PLL control node based on the operating mode. When switching from open-loop to closed-loop operation, the control node potential is changed to match the external clock frequency rather than starting at a fixed minimum frequency. This is achieved through modified charge pump switches and analog multiplexer that respond to the operational state, ensuring continuous frequency operation without jumps.
3Device complexity
If the PLL operates in open loop without frequency regulation, then the circuit implementation is simple, but the frequency cannot be smoothly tracked when switching to closed-loop operation
Solution Approach 1:
The patent applies dynamics by making the PLL control node potential adaptive rather than fixed. The modified charge pump switches and analog multiplexer enable the control node potential to dynamically adjust based on whether the PLL is in open-loop or closed-loop mode. This dynamic adjustment allows the system to maintain simplicity in implementation while achieving smooth frequency tracking when switching between operating modes, as the control node automatically assumes the appropriate potential for each mode.
Data Source
AI summary
A PLL circuit includes a phase detector, a charge pump, a filter, a voltage-controlled oscillator, and a feedback loop. The circuit further includes switch circuitry to switch between: a first PLL circuit configuration where the voltage-controlled oscillator receives a reference voltage as a voltage control signal, and the charge pump is decoupled from the phase detector, with a phase-lock control signal for oscillator regulated at the reference voltage, and a second circuit configuration where the charge pump is coupled to the phase detector and the phase-lock control signal is generated based on a phase difference detected by the phase detector and the phase-lock control signal from the charge pump is applied to the voltage-controlled oscillator as the voltage control signal.